10T SRAM Cell as an In-Memory Computing Engine for a Large Range of Boolean Computations

Abstract

The von Neumann computing architecture has been the workhorse for virtually all computing systems for the last several decades. However, it faces serious issues of memory wall problems with the ever-increasing demand for data-intensive computing systems, also known as the von Neumann bottleneck. To mitigate this bottleneck, one of the approaches that researchers have come up with is to enable in-memory Boolean computation. In this paper, in-memory computing within ten transistors (10T) SRAM bit cell array to realize any arbitrary Boolean logic in sum-of-product (SOP) form is proposed for the first time. The proposed 10T SRAM cell was designed using 45nm PTM model cards and simulated on SPICE tool. The in-memory operations were found to be accurate and robust to process variations as was observed from Monte Carlo analysis. Further, the gain we get in terms of realization of arbitrary Boolean logic overshadows the negligible increase in energy and latency compared to previous works.