An on-line error-detectable array divider with a redundant binary representation and a residue code

Abstract

An on-line error-detectable high-speed array divider is proposed. The divider is based on a formerly proposed algorithm using a redundant binary representation with a digit set (0, 1, -1). The computation time of the n-bit divider is proportional to n, in contrast to that of an array divider based on a conventional subtract-and-shift algorithm, which is proportional to n/sup 2/. By the residue checks of only the dividend, divisor, quotient, and the remainder, and a few additional checks, any error caused by a single-cell fault can be detected in normal computation. The amount of additional hardware to achieve the online error-detectability is proportional to n, and very small compared with the whole amount of hardware of the divider.<>