MRAM-based memorization system for NB-LDPC decoder

Abstract

This paper presents a novel implementation of the memorization system of the Non-Binary LDPC Decoder. The proposed approach relies on new implementations of STT-MRAM with power gating capabilities. A new data mapping has been defined to fit in with the physical dimensions of these implementations. The decoder adopting the devised memorization system has been compared to SRAM-based one which is used in almost all traditional decoders in order to demonstrate the feasibility of using power-gated MRAM. The obtained results show a significant reduction in the consumed energy by the memory reaching up to 78.45%.