Configurable multi-layer CNN-UM emulator on FPGA

Abstract

A new emulated digital multi-layer CNN-UM chip architecture called Falcon has been developed. In this paper the main steps of the FPGA implementation are introduced. Main results are as follows: CNN-UM architecture emulated on Xilinx Virtex series FPGA, 3D non-linear spatio-temporal dynamics can be implemented on this architecture. The critical parameters of the implementation in single layer configuration are 55 million cell update/second/processor core or equivalently 1 GOPS computing performance. In face of the high performance the power requirements of the architecture are relatively low only /spl sim/3 W per processor core. Using re-configurable devices to implement emulated digital architectures provides more flexibility compared to the custom VLSI designs because different Falcon architectures can be used on the same FPGA device.