A Robust and Power-Efficient Power Line Interference Canceling VLSI Design

Abstract

The electric generators functional performance is prone to suffer from harmonic distortions such as first, second, and third-order. This work proposes a low power dissipation VLSI hardware architecture for a robust power line interference canceling (PLIC). Our proposed Least Mean Square (LMS) architecture has just four clock cycles of latency per sample. The Harmonic Generator (HG) architectures are exploited and optimized in their arithmetic operations. We substituted conventional multiplier by adders and shifters, and used efficient and previously published squared multipliers. In particular, the Vedic multiplier architecture is proven to be an efficient alternative for use in the HG. Our VLSI synthesis results show that the proposed approach, combining the optimized adaptive filters LMS and HG's hardware architecture, turns the PLIC VLSI structure robust and power-efficient by effectively suppressing interferences in both ECG (Electrocardiogram) and EEG (Electroencephalo-gram) signals. Notably, the PLIC architecture is more efficient in the circuit area and power dissipation with the Vedic multiplier in the HG, with savings of up to 40% in total power and 15% in VLSI area, compared to the state-of-the-art solution.