Energy efficient fine-grain reconfigurable hardware

Abstract

In this paper a novel energy efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. The parameters of the configurable logic block architecture have been determined in order to minimize energy consumption. Circuit level low power design techniques are also applied for further reducing energy consumption. In addition, an exploration for the optimum, in terms of energy, delay and area, interconnection routing switches size has been performed.