Pub Date : 2004-05-12DOI: 10.1109/MELCON.2004.1348264
M. Imayavaramban, K. Latha, G. Uma
The aim of this paper to investigate the different schemes of matrix converter under R-L load condition and also to obtain maximum voltage transfer ratio of matrix converter. Matrix converter is a new type of direct AC/AC converter, which converts input line voltage into variable voltage with unrestricted output frequency without using intermediate circuit, DC-link circuit, pure sine-in and pure sine-out is the unique feature of the matrix converter. But maximum voltage transfer ratio of matrix converter is limited to 50%. This is the major disadvantage of matrix converter. This limitation can be overcome by eliminating third harmonics by injecting third harmonic voltage in the input voltage; the maximum voltage transfer ratio 100% is achieved. This paper also analyzes the basic operating principle and simulation modeling of different schemes of matrix converter such as 1. Two phase to single-phase matrix converter. 2. Three phase to single-phase matrix converter. 3.Three phase to three phase matrix converter using PSPICE software.
{"title":"Analysis of different schemes of matrix converter with maximum voltage conversion ratio","authors":"M. Imayavaramban, K. Latha, G. Uma","doi":"10.1109/MELCON.2004.1348264","DOIUrl":"https://doi.org/10.1109/MELCON.2004.1348264","url":null,"abstract":"The aim of this paper to investigate the different schemes of matrix converter under R-L load condition and also to obtain maximum voltage transfer ratio of matrix converter. Matrix converter is a new type of direct AC/AC converter, which converts input line voltage into variable voltage with unrestricted output frequency without using intermediate circuit, DC-link circuit, pure sine-in and pure sine-out is the unique feature of the matrix converter. But maximum voltage transfer ratio of matrix converter is limited to 50%. This is the major disadvantage of matrix converter. This limitation can be overcome by eliminating third harmonics by injecting third harmonic voltage in the input voltage; the maximum voltage transfer ratio 100% is achieved. This paper also analyzes the basic operating principle and simulation modeling of different schemes of matrix converter such as 1. Two phase to single-phase matrix converter. 2. Three phase to single-phase matrix converter. 3.Three phase to three phase matrix converter using PSPICE software.","PeriodicalId":164818,"journal":{"name":"Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115136222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-12DOI: 10.1109/MELCON.2004.1346762
V. Gradisnik, M Tomislav Pavlovic, B. Pivac, I. Zulim
In this paper the transient photo-dark current ratios (PDCR)of p-i-n a-Si:H amorphous silicon photodiode on voltage pulse at constant light and voltage pulses were measured and compared. The results show opposite PDCR behaviour of monochrome and chromatic transients in these two cases. From the measured dark current and the photocurrent, which are both proportional to the instantaneous charge change, the charge was calculated using the FFT method. The obtained results show that the depletion charge increments are much smaller than the stored ones.
{"title":"The transient photo-dark current ratio of a-Si:H p-i-n photodiode","authors":"V. Gradisnik, M Tomislav Pavlovic, B. Pivac, I. Zulim","doi":"10.1109/MELCON.2004.1346762","DOIUrl":"https://doi.org/10.1109/MELCON.2004.1346762","url":null,"abstract":"In this paper the transient photo-dark current ratios (PDCR)of p-i-n a-Si:H amorphous silicon photodiode on voltage pulse at constant light and voltage pulses were measured and compared. The results show opposite PDCR behaviour of monochrome and chromatic transients in these two cases. From the measured dark current and the photocurrent, which are both proportional to the instantaneous charge change, the charge was calculated using the FFT method. The obtained results show that the depletion charge increments are much smaller than the stored ones.","PeriodicalId":164818,"journal":{"name":"Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115705472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-12DOI: 10.1109/MELCON.2004.1346800
M. Camprini, A. Cidronali, I. Magrini, G. Collodi, L. Costanzo, G. Manes
The monolithic integration of tunneling diodes (TDs) with other conventional semiconductor devices gives the opportunity to design ultra-low DC power consumption circuits by taking advantage of the intrinsic negative differential resistance (NDR) of TDs. In this paper, we present the design of a differential oscillator based on InP-HEMT/TD technology. The circuit is based on a couple of phase-locked 5.8 GHz VCOs. Each VCO draws a current of 1.1mA at 500mV and generates an output power of -9.0 dBm on a 50/spl Omega/ load.
{"title":"Ultra low DC power consumption In-P HITFET based differential oscillator","authors":"M. Camprini, A. Cidronali, I. Magrini, G. Collodi, L. Costanzo, G. Manes","doi":"10.1109/MELCON.2004.1346800","DOIUrl":"https://doi.org/10.1109/MELCON.2004.1346800","url":null,"abstract":"The monolithic integration of tunneling diodes (TDs) with other conventional semiconductor devices gives the opportunity to design ultra-low DC power consumption circuits by taking advantage of the intrinsic negative differential resistance (NDR) of TDs. In this paper, we present the design of a differential oscillator based on InP-HEMT/TD technology. The circuit is based on a couple of phase-locked 5.8 GHz VCOs. Each VCO draws a current of 1.1mA at 500mV and generates an output power of -9.0 dBm on a 50/spl Omega/ load.","PeriodicalId":164818,"journal":{"name":"Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124405254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-12DOI: 10.1109/MELCON.2004.1347051
N. Sklavos, A. Fournaris, O. Koufopavlou
While the wireless communications are coming to offices and houses, the special needs for secure data transmission, are proved an issue of great importance. The increased number of networks subscribers, in addition to the maximized quantity of the transmitted information, has triggered the revolution of the high speed, in the transmission channel. Security in data transmission is a crucial demand, which has to be faced successfully. It is obvious that the implementation performance of security schemes is also important as the offered security level itself. In this work, the implementation cost and the performance evaluation of RC5 implementations is presented. This cipher is adopted by a great number of wireless protocols, such as WAP. The FPGA implementation synthesis results for a scalable architecture are shown, for a scalable proposed architecture. Alternative adders and subtracters designs are examined for the system architecture, in order high performance and low area resources to be achieved.
{"title":"WAP security: implementation cost and performance evaluation of a scalable architecture for RC5 parameterized block cipher","authors":"N. Sklavos, A. Fournaris, O. Koufopavlou","doi":"10.1109/MELCON.2004.1347051","DOIUrl":"https://doi.org/10.1109/MELCON.2004.1347051","url":null,"abstract":"While the wireless communications are coming to offices and houses, the special needs for secure data transmission, are proved an issue of great importance. The increased number of networks subscribers, in addition to the maximized quantity of the transmitted information, has triggered the revolution of the high speed, in the transmission channel. Security in data transmission is a crucial demand, which has to be faced successfully. It is obvious that the implementation performance of security schemes is also important as the offered security level itself. In this work, the implementation cost and the performance evaluation of RC5 implementations is presented. This cipher is adopted by a great number of wireless protocols, such as WAP. The FPGA implementation synthesis results for a scalable architecture are shown, for a scalable proposed architecture. Alternative adders and subtracters designs are examined for the system architecture, in order high performance and low area resources to be achieved.","PeriodicalId":164818,"journal":{"name":"Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121273331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-12DOI: 10.1109/MELCON.2004.1347054
A. Moldovyan, N. A. Moldovyan, N. Sklavos
This work focuses the problem of increasing the performance of the ciphers based on data-dependent (DD) operations (DDO) for VLSI implementations. New minimum size primitives are proposed to design DDOs. Using advanced DDOs instead of DD permutations (DDP) in the DDP-based iterative ciphers Cobra-H64 and Cobra H128 the number of rounds has been significantly reduced yielding enhancement of the "performance per cost" value. To obtain further enhancement of this parameter a new crypto-scheme based on the advanced DDOs is proposed. The FPGA implementation of the proposed crypto-scheme achieves higher throughput value and minimizes the allocated resources than the conventional designs.
{"title":"Minimum size primitives for efficient VLSI implementation of DDO-based ciphers","authors":"A. Moldovyan, N. A. Moldovyan, N. Sklavos","doi":"10.1109/MELCON.2004.1347054","DOIUrl":"https://doi.org/10.1109/MELCON.2004.1347054","url":null,"abstract":"This work focuses the problem of increasing the performance of the ciphers based on data-dependent (DD) operations (DDO) for VLSI implementations. New minimum size primitives are proposed to design DDOs. Using advanced DDOs instead of DD permutations (DDP) in the DDP-based iterative ciphers Cobra-H64 and Cobra H128 the number of rounds has been significantly reduced yielding enhancement of the \"performance per cost\" value. To obtain further enhancement of this parameter a new crypto-scheme based on the advanced DDOs is proposed. The FPGA implementation of the proposed crypto-scheme achieves higher throughput value and minimizes the allocated resources than the conventional designs.","PeriodicalId":164818,"journal":{"name":"Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126645165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-12DOI: 10.1109/MELCON.2004.1347005
I. Roussaki, M. Louta, L. Pechlivanos
E-commerce is expected to dominate the market if coupled with the appropriate technologies and mechanisms. Mobile agents are one of the means that may enhance the intelligence and improve the computational efficiency of systems in the e-marketplace. In this paper, we propose a dynamic multilateral negotiation model that can be used to extend the functionality of autonomous agents, so that they can reach an agreement that maximises their owner's utility. The model considers both the contract and decision issues based on the real market conditions and has been empirically evaluated.
{"title":"An efficient negotiation model for the next generation electronic marketplace","authors":"I. Roussaki, M. Louta, L. Pechlivanos","doi":"10.1109/MELCON.2004.1347005","DOIUrl":"https://doi.org/10.1109/MELCON.2004.1347005","url":null,"abstract":"E-commerce is expected to dominate the market if coupled with the appropriate technologies and mechanisms. Mobile agents are one of the means that may enhance the intelligence and improve the computational efficiency of systems in the e-marketplace. In this paper, we propose a dynamic multilateral negotiation model that can be used to extend the functionality of autonomous agents, so that they can reach an agreement that maximises their owner's utility. The model considers both the contract and decision issues based on the real market conditions and has been empirically evaluated.","PeriodicalId":164818,"journal":{"name":"Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115184828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-12DOI: 10.1109/MELCON.2004.1348273
A.A. Muhammad, G.I. Aziz
In this work we present a locally developed integrated optics technology for the fabrication and characterization of integrated optical components. The fabrication was carried out using the ion exchange in glass. Both single mode guides and multi-mode interference MMI splitter are, for the first time in Egypt, fabricated and tested. For the characterization purpose, an automated setup is developed in order to scan for the reflection sites within the integrated optical structures.
{"title":"Single mode channel waveguide and MMI beam splitter fabrication and characterization","authors":"A.A. Muhammad, G.I. Aziz","doi":"10.1109/MELCON.2004.1348273","DOIUrl":"https://doi.org/10.1109/MELCON.2004.1348273","url":null,"abstract":"In this work we present a locally developed integrated optics technology for the fabrication and characterization of integrated optical components. The fabrication was carried out using the ion exchange in glass. Both single mode guides and multi-mode interference MMI splitter are, for the first time in Egypt, fabricated and tested. For the characterization purpose, an automated setup is developed in order to scan for the reflection sites within the integrated optical structures.","PeriodicalId":164818,"journal":{"name":"Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116002890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-12DOI: 10.1109/MELCON.2004.1346959
T. Detert, W. Haak, I. Martoyo
In this paper, a performance comparison of orthogonal variable spreading factor (OVSF) codes and complete complementary (CC) channelization codes in Rayleigh fading channels is presented in the uplink. The bit error rate (BER) is simulated to provide a means of comparison for different spreading factors (SF) and different numbers of users. The system is totally asynchronous, and a special simulation strategy is applied to make the simulation of long scrambling codes possible. An introduction to the correlation functions utilized in the computation of the multiple access interference (MAI) seen by each user is given. Except the application of CC-codes, the simulation strictly sticks to the UTRA FDD standard.
{"title":"Complete complementary codes applied to UTRA FDD asynchronous uplink","authors":"T. Detert, W. Haak, I. Martoyo","doi":"10.1109/MELCON.2004.1346959","DOIUrl":"https://doi.org/10.1109/MELCON.2004.1346959","url":null,"abstract":"In this paper, a performance comparison of orthogonal variable spreading factor (OVSF) codes and complete complementary (CC) channelization codes in Rayleigh fading channels is presented in the uplink. The bit error rate (BER) is simulated to provide a means of comparison for different spreading factors (SF) and different numbers of users. The system is totally asynchronous, and a special simulation strategy is applied to make the simulation of long scrambling codes possible. An introduction to the correlation functions utilized in the computation of the multiple access interference (MAI) seen by each user is given. Except the application of CC-codes, the simulation strictly sticks to the UTRA FDD standard.","PeriodicalId":164818,"journal":{"name":"Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116394463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-12DOI: 10.1109/MELCON.2004.1348218
A. Pavić, M. Stojkov, K. Trupinić
The main goal of this paper is initiation of the method for determination of possible stealing of electrical energy and for estimation of exact length location of illegal connection. Method is based on time domain reflectometer (TDR) principles and function.
{"title":"Illegal connection location on main power cable","authors":"A. Pavić, M. Stojkov, K. Trupinić","doi":"10.1109/MELCON.2004.1348218","DOIUrl":"https://doi.org/10.1109/MELCON.2004.1348218","url":null,"abstract":"The main goal of this paper is initiation of the method for determination of possible stealing of electrical energy and for estimation of exact length location of illegal connection. Method is based on time domain reflectometer (TDR) principles and function.","PeriodicalId":164818,"journal":{"name":"Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114467474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-12DOI: 10.1109/MELCON.2004.1346786
D. Grzechca, J. Rutkowski
This paper presents research on analog fault detection and location. The problem of distinguishing between healthy and faulty analog circuits has always been very complicated. Moreover, if a test locates a faulty element, a great problem occurs. The most common approach based on pattern recognition, especially on mean square error measure, cannot distinguish all faulty circuits from healthy ones. Normally, the dictionary has to include thousands of patterns and even then, the level of fault detection/location is not satisfactory. A neutral network classifier has been proposed to solve the problem. Its generalization ability allows reducing the dictionary size significantly. This paper shows how to create a neutral dictionary test for detection and location. Moreover, at the first stage of classification, the fuzzy logic is utilized to transform a measurement vector into a zero - one range (a continuous value). Output of a neutral network is coded. It reduces the number of output neutrons.
{"title":"New concept to analog fault diagnosis by creating two fuzzy-neutral dictionaries test","authors":"D. Grzechca, J. Rutkowski","doi":"10.1109/MELCON.2004.1346786","DOIUrl":"https://doi.org/10.1109/MELCON.2004.1346786","url":null,"abstract":"This paper presents research on analog fault detection and location. The problem of distinguishing between healthy and faulty analog circuits has always been very complicated. Moreover, if a test locates a faulty element, a great problem occurs. The most common approach based on pattern recognition, especially on mean square error measure, cannot distinguish all faulty circuits from healthy ones. Normally, the dictionary has to include thousands of patterns and even then, the level of fault detection/location is not satisfactory. A neutral network classifier has been proposed to solve the problem. Its generalization ability allows reducing the dictionary size significantly. This paper shows how to create a neutral dictionary test for detection and location. Moreover, at the first stage of classification, the fuzzy logic is utilized to transform a measurement vector into a zero - one range (a continuous value). Output of a neutral network is coded. It reduces the number of output neutrons.","PeriodicalId":164818,"journal":{"name":"Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114547700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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