A novel low power low voltage full adder cell

Abstract

The power-delay product is a direct measurement of the energy expended per operational cycle of an arithmetic circuit. Lowering the supply voltage of the full adder cell to achieve low power-delay product is a sensible approach to dramatically improve the power efficiency at sustainable speed of arithmetic circuits composed of such instances at high level design. In this paper, a novel design of a low power 1-bit full adder cell is proposed where the simultaneous generation of XOR and XNOR outputs by pass logic is exploited but with swing restoration circuit added to make ultra low voltage operation down to 0.5 V feasible. A novel complementary CMOS carry generation circuit is devised to produce full-swing and balanced outputs with strong drivability. Simulation results show that our full adder circuit outstrips many latest designs in energy efficiency and has the lowest power-delay product over a wide range of voltages among several low power adder cells of different CMOS logic styles.