PATIS: Using partial configuration to improve static FPGA design productivity

T. Frangieh, A. Chandrasekharan, S. Rajagopalan, Yousef Iskander, S. Craven, C. Patterson
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引用次数: 15

Abstract

Reconfigurable hardware development and debugging tools aspire to provide software-like productivity. A major impediment, however, is the lack of a module linkage capability permitting hardware blocks to be compiled concurrently, limiting the effective use of multi-core and multiprocessor platforms. Although modular and incremental design flows can reuse the layouts of unmodified blocks, non-local changes to the logical hierarchy or physical layout, or addition of debug circuitry, generally force complete re-implementation. We describe the PATIS dynamic floorplanner, targeting development environments in which some circuit speed and area optimization may be sacrificed for improved implementation and debug turnaround. The floorplan consists of partial modules with structured physical interfaces observable through configuration readback rather than synthesized logic analysis circuitry, allowing module ports to be passively probed without disturbing the layout. Although PATIS supports incremental design, complete re-implementation is still rapid because the partial bitstream for each block is generated by independent and concurrent invocations of the standard Xilinx tools running on separate cores or hosts. A continuous background task proactively generates floorplan variants to accelerate global layout changes. The partial reconfiguration design flow is easier to automate in PATIS because run-time module swapping is not required, suggesting that partial reconfiguration may serve a useful role in large-scale static design.
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PATIS:使用局部配置来提高静态FPGA设计效率
可重构硬件开发和调试工具渴望提供类似软件的生产力。然而,一个主要的障碍是缺乏允许硬件块并发编译的模块链接能力,限制了多核和多处理器平台的有效使用。尽管模块化和增量设计流可以重用未修改块的布局,但对逻辑层次结构或物理布局的非局部更改,或添加调试电路,通常会强制完全重新实现。我们描述了PATIS动态平面图,针对开发环境,其中一些电路速度和面积优化可能会牺牲改进的实现和调试周转。平面图由部分模块组成,这些模块具有结构化的物理接口,可以通过配置回读而不是合成逻辑分析电路来观察,从而允许在不干扰布局的情况下被动探测模块端口。尽管PATIS支持增量设计,但完全重新实现仍然很快,因为每个块的部分比特流是由运行在单独核心或主机上的标准Xilinx工具的独立和并发调用生成的。持续的后台任务主动生成平面图变体,以加速全局布局的变化。部分重新配置设计流更容易在PATIS中实现自动化,因为不需要运行时模块交换,这表明部分重新配置可能在大规模静态设计中发挥有用的作用。
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