Pub Date : 2022-07-29DOI: 10.1109/IPDPSW.2010.5470681
J. Becker, E. Bozorgzadeh, João MP Cardoso, A. Dasu
The 17th Reconfigurable Architectures Workshop (RAW 2010) is being held in Atlanta, USA in April 2010. As usual, RAW is associated with the Annual International Parallel & Distributed Processing Symposium (IPDPS) and is sponsored by the IEEE Computer Society's Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers and practitioners to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.
{"title":"Welcome message","authors":"J. Becker, E. Bozorgzadeh, João MP Cardoso, A. Dasu","doi":"10.1109/IPDPSW.2010.5470681","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470681","url":null,"abstract":"The 17th Reconfigurable Architectures Workshop (RAW 2010) is being held in Atlanta, USA in April 2010. As usual, RAW is associated with the Annual International Parallel & Distributed Processing Symposium (IPDPS) and is sponsored by the IEEE Computer Society's Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers and practitioners to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130820053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-24DOI: 10.1109/IPDPSW.2010.5470737
C. Ulmer, M. Gokhale
This paper describes our approach to adapting a text document similarity classifier based on the Term Frequency Inverse Document Frequency (TFIDF) metric [11] to reconfigurable hardware. The TFIDF classifier is used to detect web attacks in HTTP data. In our reconfigurable hardware approach, we design a streaming, real-time classifier by simplifying an existing sequential algorithm and manipulating the classifier's model to allow decision information to be represented compactly. We have developed a set of software tools to help automate the process of converting training data to synthesizable hardware and to provide a means of trading off between accuracy and resource utilization. The Xilinx Virtex 5-LX implementation requires two orders of magnitude less memory than the original algorithm. At 166MB/s (80X the software) the hardware implementation is able to achieve Gigabit network throughput at the same accuracy as the original algorithm.
{"title":"A configurable-hardware document-similarity classifier to detect web attacks","authors":"C. Ulmer, M. Gokhale","doi":"10.1109/IPDPSW.2010.5470737","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470737","url":null,"abstract":"This paper describes our approach to adapting a text document similarity classifier based on the Term Frequency Inverse Document Frequency (TFIDF) metric [11] to reconfigurable hardware. The TFIDF classifier is used to detect web attacks in HTTP data. In our reconfigurable hardware approach, we design a streaming, real-time classifier by simplifying an existing sequential algorithm and manipulating the classifier's model to allow decision information to be represented compactly. We have developed a set of software tools to help automate the process of converting training data to synthesizable hardware and to provide a means of trading off between accuracy and resource utilization. The Xilinx Virtex 5-LX implementation requires two orders of magnitude less memory than the original algorithm. At 166MB/s (80X the software) the hardware implementation is able to achieve Gigabit network throughput at the same accuracy as the original algorithm.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"758 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132902547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-24DOI: 10.1109/IPDPSW.2010.5470771
Guojing Cong, I. Chung, H. Wen, D. Klepacki, H. Murata, Yasushi Negishi, T. Moriyama
To fully utilize the power of current high performance computing systems, high productivity to the end user is critical. It is a challenge to map an application to the target architecture efficiently. Tuning an application for high performance remains a daunting task, and frequently involves manual changes to the program. Recently refactoring techniques are proposed to rewrite or reorganize programs for various software engineering purposes. In our research we explore combining performance analysis with refactoring techniques for automated tuning that we expect to greatly improve the productivity of application deployment. We seek to build a system that can apply appropriate refactoring according to the bottleneck discovered. We demonstrate the effectiveness of this approach through the tuning of several scientific applications and kernels.
{"title":"Application tuning through bottleneck-driven refactoring","authors":"Guojing Cong, I. Chung, H. Wen, D. Klepacki, H. Murata, Yasushi Negishi, T. Moriyama","doi":"10.1109/IPDPSW.2010.5470771","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470771","url":null,"abstract":"To fully utilize the power of current high performance computing systems, high productivity to the end user is critical. It is a challenge to map an application to the target architecture efficiently. Tuning an application for high performance remains a daunting task, and frequently involves manual changes to the program. Recently refactoring techniques are proposed to rewrite or reorganize programs for various software engineering purposes. In our research we explore combining performance analysis with refactoring techniques for automated tuning that we expect to greatly improve the productivity of application deployment. We seek to build a system that can apply appropriate refactoring according to the bottleneck discovered. We demonstrate the effectiveness of this approach through the tuning of several scientific applications and kernels.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115022580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-04-19DOI: 10.1109/IPDPSW.2010.5470826
O. Ibarra
The past twenty years have seen a flurry of activity in the arena of parallel and distributed computing. In recent years, novel parallel and distributed computational models have been proposed in the literature, reflecting advances in new computational devices and environments such as optical interconnects, programmable logic arrays, networks of workstations, radio communications, mobile computing, DNA computing, quantum computing, sensor networks etc. It is very encouraging to note that the advent of these new models has lead to significant advances in the resolution of various difficult problems of practical interest. The main goal of this workshop is to provide a timely forum for the exchange and dissemination of new ideas, techniques and research in the field of the parallel and distributed computational models. The workshop is meant to bring together researchers and practitioners interested in all aspects of parallel and distributed computing taken in an inclusive, rather than exclusive, sense. We are convinced that the workshop atmosphere will be conducive to open and mutually beneficial exchanges of ideas between the participants.
{"title":"Advances in parallel and distributed computing models - APDCM","authors":"O. Ibarra","doi":"10.1109/IPDPSW.2010.5470826","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470826","url":null,"abstract":"The past twenty years have seen a flurry of activity in the arena of parallel and distributed computing. In recent years, novel parallel and distributed computational models have been proposed in the literature, reflecting advances in new computational devices and environments such as optical interconnects, programmable logic arrays, networks of workstations, radio communications, mobile computing, DNA computing, quantum computing, sensor networks etc. It is very encouraging to note that the advent of these new models has lead to significant advances in the resolution of various difficult problems of practical interest. The main goal of this workshop is to provide a timely forum for the exchange and dissemination of new ideas, techniques and research in the field of the parallel and distributed computational models. The workshop is meant to bring together researchers and practitioners interested in all aspects of parallel and distributed computing taken in an inclusive, rather than exclusive, sense. We are convinced that the workshop atmosphere will be conducive to open and mutually beneficial exchanges of ideas between the participants.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114647357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-04-19DOI: 10.1109/IPDPSW.2010.5470944
Pritish Jetley, L. Kalé
The expression of parallel codes through abstract, high-level specifications of global control and data flow can greatly simplify the task of creating large parallel programs. We discuss the challenges of compiling such global flows into the behavioral descriptions of individual component objects in an SPMD environment. We present our work in the context of Charisma, a language that describes global data and control flow through a simple script-like language. Inter-object interactions are realized through the production and consumption of data. The compiler infers communication patterns between objects and generates appropriate messaging code. We discuss the productivity and performance benefits of compiling such global specifications into local descriptions of control flow embodied by a language called Structured Dagger (SDAG).
{"title":"Static macro data flow: Compiling global control into local control","authors":"Pritish Jetley, L. Kalé","doi":"10.1109/IPDPSW.2010.5470944","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470944","url":null,"abstract":"The expression of parallel codes through abstract, high-level specifications of global control and data flow can greatly simplify the task of creating large parallel programs. We discuss the challenges of compiling such global flows into the behavioral descriptions of individual component objects in an SPMD environment. We present our work in the context of Charisma, a language that describes global data and control flow through a simple script-like language. Inter-object interactions are realized through the production and consumption of data. The compiler infers communication patterns between objects and generates appropriate messaging code. We discuss the productivity and performance benefits of compiling such global specifications into local descriptions of control flow embodied by a language called Structured Dagger (SDAG).","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125107899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-04-19DOI: 10.1109/IPDPSW.2010.5470711
Florent Blachot, Guillaume Huard, Johnatan E. Pecero, Erik Saule, D. Trystram
The aim of this work is to study the problem of scheduling fine grain task graphs on hierarchical distributed systems with communication delay. We consider as a case study how to schedule the instructions on a processor that implements incomplete bypass ( ST200). We show first how this problem can be expressed as scheduling unitary tasks on a hierarchical architecture with heavy communications between clustered units. The proposed analysis is generic and can be extended to other challenging problems like scheduling in clusters of multi-cores. Our main result is an approximation algorithm based on list scheduling whose approximation ratio is the minimum of two expressions, the first one depends on the number of clusters while the second one depends on the communication delay. Experiments run on random graphs and on structured graphs demonstrate the effectiveness of the proposed approach.
{"title":"Scheduling instructions on hierarchical machines","authors":"Florent Blachot, Guillaume Huard, Johnatan E. Pecero, Erik Saule, D. Trystram","doi":"10.1109/IPDPSW.2010.5470711","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470711","url":null,"abstract":"The aim of this work is to study the problem of scheduling fine grain task graphs on hierarchical distributed systems with communication delay. We consider as a case study how to schedule the instructions on a processor that implements incomplete bypass ( ST200). We show first how this problem can be expressed as scheduling unitary tasks on a hierarchical architecture with heavy communications between clustered units. The proposed analysis is generic and can be extended to other challenging problems like scheduling in clusters of multi-cores. Our main result is an approximation algorithm based on list scheduling whose approximation ratio is the minimum of two expressions, the first one depends on the number of clusters while the second one depends on the communication delay. Experiments run on random graphs and on structured graphs demonstrate the effectiveness of the proposed approach.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125931045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-04-19DOI: 10.1109/IPDPSW.2010.5470808
B. Fateh, G. Manimaran
We consider the problem of energy-aware joint scheduling of tasks and messages with real-time constraints in wireless networked embedded systems specifically wireless sensor networks. We use the mixed tree coloring approach in order to model the constraints and show that k-coloring of a mixed tree can be mapped to a non-conflicting schedule consisting of k time slots. Also, we propose to conduct testbed evaluation to quantify the performance of combined implementation of energy management techniques such as Dynamic Modulation Scaling (DMS) along with Dynamic Voltage Scaling (DVS).
{"title":"Energy-aware joint scheduling of tasks and messages in wireless sensor networks","authors":"B. Fateh, G. Manimaran","doi":"10.1109/IPDPSW.2010.5470808","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470808","url":null,"abstract":"We consider the problem of energy-aware joint scheduling of tasks and messages with real-time constraints in wireless networked embedded systems specifically wireless sensor networks. We use the mixed tree coloring approach in order to model the constraints and show that k-coloring of a mixed tree can be mapped to a non-conflicting schedule consisting of k time slots. Also, we propose to conduct testbed evaluation to quantify the performance of combined implementation of energy management techniques such as Dynamic Modulation Scaling (DMS) along with Dynamic Voltage Scaling (DVS).","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123752885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-04-19DOI: 10.1109/IPDPSW.2010.5470786
Nikos Tziritas, Thanasis Loukopoulos, S. Lalis, P. Lampsas
Embedded applications can be structured in terms of mobile agents that are flexibly installed on available nodes. In wireless systems, such nodes typically have limited battery and memory resources; therefore it is important to place agents judiciously. In this paper we tackle the problem of placing a newcomer agent in such a system. The problem has two main components. First, enough memory space must be found or created at some node to place the agent. Second, the placement should be energy efficient. We present heuristics for tackling these two goals in a stepwise fashion, as well as a branch and bound method for achieving both goals at the same time. Our algorithms are centralized assuming a single entry point through which agents are injected into the system, with adequate knowledge of the system state and enough resources to run the proposed algorithms. The algorithms are evaluated under different simulated scenarios, and the tradeoffs across the two metrics (space, energy) are identified.
{"title":"Agent placement in wireless embedded systems: Memory space and energy optimizations","authors":"Nikos Tziritas, Thanasis Loukopoulos, S. Lalis, P. Lampsas","doi":"10.1109/IPDPSW.2010.5470786","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470786","url":null,"abstract":"Embedded applications can be structured in terms of mobile agents that are flexibly installed on available nodes. In wireless systems, such nodes typically have limited battery and memory resources; therefore it is important to place agents judiciously. In this paper we tackle the problem of placing a newcomer agent in such a system. The problem has two main components. First, enough memory space must be found or created at some node to place the agent. Second, the placement should be energy efficient. We present heuristics for tackling these two goals in a stepwise fashion, as well as a branch and bound method for achieving both goals at the same time. Our algorithms are centralized assuming a single entry point through which agents are injected into the system, with adequate knowledge of the system state and enough resources to run the proposed algorithms. The algorithms are evaluated under different simulated scenarios, and the tradeoffs across the two metrics (space, energy) are identified.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125283710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-04-19DOI: 10.1109/IPDPSW.2010.5470828
S. Grumbach, Zhilin Wu
The tree decomposition of graphs is a fundamental algorithmic tool. It has been shown that difficult problems, such as some NP-complete ones, can be solved efficiently over classes of graphs of bounded tree-width. We consider in this paper the distributed construction of the tree decompositions of network topology graphs. We propose algorithms to distributively construct the tree-decomposition of respectively (i) planar networks of bounded diameter and (ii) networks of bounded degree and bounded tree-length. Both algorithms are very efficient, requiring only a constant number of messages sent over each link. We then use these algorithms to distributively verify properties of graphs expressible in Monadic Second Order Logic, MSO.
{"title":"Distributed tree decomposition of graphs and applications to verification","authors":"S. Grumbach, Zhilin Wu","doi":"10.1109/IPDPSW.2010.5470828","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470828","url":null,"abstract":"The tree decomposition of graphs is a fundamental algorithmic tool. It has been shown that difficult problems, such as some NP-complete ones, can be solved efficiently over classes of graphs of bounded tree-width. We consider in this paper the distributed construction of the tree decompositions of network topology graphs. We propose algorithms to distributively construct the tree-decomposition of respectively (i) planar networks of bounded diameter and (ii) networks of bounded degree and bounded tree-length. Both algorithms are very efficient, requiring only a constant number of messages sent over each link. We then use these algorithms to distributively verify properties of graphs expressible in Monadic Second Order Logic, MSO.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125518938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-04-19DOI: 10.1109/IPDPSW.2010.5470880
Jiong Xie, Shu Yin, X. Ruan, Zhiyang Ding, Yun Tian, James Majors, A. Manzanares, X. Qin
MapReduce has become an important distributed processing model for large-scale data-intensive applications like data mining and web indexing. Hadoop-an open-source implementation of MapReduce is widely used for short jobs requiring low response time. The current Hadoop implementation assumes that computing nodes in a cluster are homogeneous in nature. Data locality has not been taken into account for launching speculative map tasks, because it is assumed that most maps are data-local. Unfortunately, both the homogeneity and data locality assumptions are not satisfied in virtualized data centers. We show that ignoring the data-locality issue in heterogeneous environments can noticeably reduce the MapReduce performance. In this paper, we address the problem of how to place data across nodes in a way that each node has a balanced data processing load. Given a dataintensive application running on a Hadoop MapReduce cluster, our data placement scheme adaptively balances the amount of data stored in each node to achieve improved data-processing performance. Experimental results on two real data-intensive applications show that our data placement strategy can always improve the MapReduce performance by rebalancing data across nodes before performing a data-intensive application in a heterogeneous Hadoop cluster.
{"title":"Improving MapReduce performance through data placement in heterogeneous Hadoop clusters","authors":"Jiong Xie, Shu Yin, X. Ruan, Zhiyang Ding, Yun Tian, James Majors, A. Manzanares, X. Qin","doi":"10.1109/IPDPSW.2010.5470880","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470880","url":null,"abstract":"MapReduce has become an important distributed processing model for large-scale data-intensive applications like data mining and web indexing. Hadoop-an open-source implementation of MapReduce is widely used for short jobs requiring low response time. The current Hadoop implementation assumes that computing nodes in a cluster are homogeneous in nature. Data locality has not been taken into account for launching speculative map tasks, because it is assumed that most maps are data-local. Unfortunately, both the homogeneity and data locality assumptions are not satisfied in virtualized data centers. We show that ignoring the data-locality issue in heterogeneous environments can noticeably reduce the MapReduce performance. In this paper, we address the problem of how to place data across nodes in a way that each node has a balanced data processing load. Given a dataintensive application running on a Hadoop MapReduce cluster, our data placement scheme adaptively balances the amount of data stored in each node to achieve improved data-processing performance. Experimental results on two real data-intensive applications show that our data placement strategy can always improve the MapReduce performance by rebalancing data across nodes before performing a data-intensive application in a heterogeneous Hadoop cluster.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125550125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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