Design high performance and low power 10T full adder cell using double gate MOSFET at 45nm technology

Abstract

Design of complex arithmetic logic circuits considering leakage current, active power and delay is an important and challenging task in deep submicron circuits. Double gate transistor circuit consider as a promising candidate for low power application domain as well as used in Radio Frequency (RF) devices. In this paper we designed full adder with the help of double gate transistor, the used parameters value has been varied significantly thus improving the performance of full adder. Power Gating is one of the most used circuit techniques to reduce the leakage current in idle circuit. In this paper different parameters are analysed on Power Gating Technique. Power Gating technique achieves 93% reduction of leakage current, active power is reduced by 60% and delay is reduced by 14% as compared with conventional double gate full adder. Simulation results of double gate full adder have been performed on cadence virtuoso with 45nm technology.