Cache coherency controller verification IP using SystemVerilog Assertions (SVA) and Universal Verification Methodologies (UVM)

Abstract

Shared memory resources are inevitable components in modern SOC architecture due to Multi-core Architectures resulting ease synchronization with enhanced speed and reliability. Again architectural verification are challenging for these protocols for coherency systems. Hence this project work has come out with complete verification environment for such a complex MESI coherency protocol based on model checking and assumes guarantee verification methods developed through compositional approach of SystemVerilog Assertions (SVA) with functional verification using Universal Verification Methodologies (UVM) packages to substantially ameliorate the difficulties for design accuracy.