{"title":"FPGA based design of multifunction ALU","authors":"Anup Kumar, Manish Kumar, G. Jha, Kriti Suneja","doi":"10.1109/CCICT53244.2021.00025","DOIUrl":null,"url":null,"abstract":"With the growing need of fast arithmetic calculations, Field Programmable Gate Arrays (FPGAs) have shown the promising results. To take this idea further, we have implemented five functions which are of immense use in digital signal processing, communication, encryption, etc. applications. The simulations have been performed in Xilinx Vivado and the target device for synthesis results belongs to Kintex FPGA family. The simulation results are in good agreement with the theory and synthesis results show the device utilization in the form of Look Up tables, an indicator of area used. The comparison among different implemented functions shows that while average requires least number of LUTs, circular convolution requires most.","PeriodicalId":213095,"journal":{"name":"2021 Fourth International Conference on Computational Intelligence and Communication Technologies (CCICT)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 Fourth International Conference on Computational Intelligence and Communication Technologies (CCICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCICT53244.2021.00025","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
With the growing need of fast arithmetic calculations, Field Programmable Gate Arrays (FPGAs) have shown the promising results. To take this idea further, we have implemented five functions which are of immense use in digital signal processing, communication, encryption, etc. applications. The simulations have been performed in Xilinx Vivado and the target device for synthesis results belongs to Kintex FPGA family. The simulation results are in good agreement with the theory and synthesis results show the device utilization in the form of Look Up tables, an indicator of area used. The comparison among different implemented functions shows that while average requires least number of LUTs, circular convolution requires most.