Low-power CMOS folding and interpolating ADC with a fully-folding technique

Abstract

A 8-bit 150 MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-folding technique is designed in a 0.35 mum standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one and in bit synchronization block to reduce the number of comparators for low power. A novel bit synchronization architecture based on folding circuits is presented. A low-power encoder using a novel arithmetic is adopted. The total power dissipation is merely 65 mW at a 3.3 V supply.