Multi-level signaling for energy-efficient on-chip interconnects

Abstract

In this paper, we develop multi-level signaling schemes for on-chip interconnects in order to achieve energy-efficient communication. The methodology uses both bus multiplexing and low-swing signaling characteristics, while keeping the total bus area fixed. A physics-based energy model for coupling capacitance is developed which accurately captures the energy consumption of very deep sub-micron (VDSM) on-chip interconnect in the context of multi-level signals. Results show that our proposed bus achieves energy savings for intermediate-layer interconnect lines of as much as 76% compared to binary signaling. In addition, wire bandwidth is improved by up to 16% compared to prior approaches.