Ultra-Low-k interlayer dielectric for post-moore CMOS interconnect

Abstract

This paper gives a general overview on the methods to reduce interconnect resistance and capacitance in a standard CMOS technology followed by a discussion on the physical constraints that dictate the minimum achievable loading. A newly demonstrated method that uses carbon-nanotube to assist the formation of vertically aligned porous structure is studied. The method was shown to be able to reduce the dielectric constant of the interlayer dielectric to an extremely low value below 2.0 with reasonable physical strength. The potential of this method to be used in main-stream production technology is investigated.