S. Fung, N. Zamdmer, P. Oldiges, J. Sleight, A. Mocuta, M. Sherony, S.-H. Lo, R. Joshi, C. Chuang, I. Yang, S. Crowder, T. Chen, F. Assaderaghi, G. Shahidi
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引用次数: 25
Abstract
The ultra-thin gate oxide required for the 0.13 /spl mu/m generation and beyond introduces a significant amount of gate-to-body tunneling current. The gate current modulates the body voltage and therefore the history effect. This paper discusses several methods to minimize the impact of gate current, which can cause excessive history effect in 0.10 /spl mu/m SOI CMOS. Our result demonstrates that the combination of high gate leakage and small junction capacitance can enhance circuit performance due to beneficial gate coupling. Ultra-low junction capacitance can be achieved by aggressive SOI thickness scaling, though, the proximity of source/drain extension and channel depletion to the buried oxide complicates device design and modeling.
0.13 /spl mu/m及以上一代所需的超薄栅极氧化物引入了大量的栅极到体隧穿电流。栅极电流调制体电压,从而调制历史效应。本文讨论了几种减小栅极电流影响的方法,栅极电流在0.10 /spl μ l /m SOI CMOS中会造成过大的历史效应。我们的研究结果表明,高栅漏和小结电容的结合可以提高电路的性能,因为有利的栅极耦合。超低结电容可以通过积极的SOI厚度缩放来实现,但是,源/漏极扩展和通道耗尽与埋藏氧化物的接近使器件设计和建模变得复杂。