Pub Date : 2000-12-12DOI: 10.1109/IEDM.2000.904364
V. Nguyen, P. van der Velden, R. Daamen, H. van Kranenburg, P. Woerlee
In this paper, a physical model for the development of dishing during metal chemical mechanical polishing (CMP) is proposed. The main assumption of the model is that material removal occurs predominantly at the pad/wafer contacts. The distribution of pad/wafer contact size is studied first. This distribution is used as an input for a model of the dependence for the material removal rate on the line width. A relation that describes the development of dishing as a function of overpolish time will be presented. The model describes to a great accuracy the observed dishing effects, using one free parameter.
{"title":"Modelling of dishing for metal chemical mechanical polishing","authors":"V. Nguyen, P. van der Velden, R. Daamen, H. van Kranenburg, P. Woerlee","doi":"10.1109/IEDM.2000.904364","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904364","url":null,"abstract":"In this paper, a physical model for the development of dishing during metal chemical mechanical polishing (CMP) is proposed. The main assumption of the model is that material removal occurs predominantly at the pad/wafer contacts. The distribution of pad/wafer contact size is studied first. This distribution is used as an input for a model of the dependence for the material removal rate on the line width. A relation that describes the development of dishing as a function of overpolish time will be presented. The model describes to a great accuracy the observed dishing effects, using one free parameter.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128082534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904362
Jun‐Bo Yoon, C. Nguyen
A high-Q, tunable, micromechanical capacitor has been realized using an IC-compatible, electroplated-metal surface micromachining technology and demonstrated with quality (Q-) factors in excess of 290-the highest reported to date for on-chip tunable capacitors at frequencies near 1 GHz. The key feature in this design that makes possible such high on-chip Q is the method for capacitive tuning, which in this design is based on moving the dielectric between the capacitor plates, rather than moving the plates themselves, as done in previous designs. One version of this design achieves a measured Q of 291 at 1 GHz (C=1.21 pF) with a tuning range of 7.7% over 10 V of control voltage, and an expected self-resonant frequency (SRF) of 19 GHz. In another design, with a wider tuning range of 40% over 10 V, a Q of 218 is achieved at 1 GHz (C=1.14 pF).
{"title":"A high-Q tunable micromechanical capacitor with movable dielectric for RF applications","authors":"Jun‐Bo Yoon, C. Nguyen","doi":"10.1109/IEDM.2000.904362","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904362","url":null,"abstract":"A high-Q, tunable, micromechanical capacitor has been realized using an IC-compatible, electroplated-metal surface micromachining technology and demonstrated with quality (Q-) factors in excess of 290-the highest reported to date for on-chip tunable capacitors at frequencies near 1 GHz. The key feature in this design that makes possible such high on-chip Q is the method for capacitive tuning, which in this design is based on moving the dielectric between the capacitor plates, rather than moving the plates themselves, as done in previous designs. One version of this design achieves a measured Q of 291 at 1 GHz (C=1.21 pF) with a tuning range of 7.7% over 10 V of control voltage, and an expected self-resonant frequency (SRF) of 19 GHz. In another design, with a wider tuning range of 40% over 10 V, a Q of 218 is achieved at 1 GHz (C=1.14 pF).","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117274036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904389
O. Wada
Ultrafast optoelectronic devices are crucial for fulfilling the future requirement of communication network throughput to enter the 1 Tb/s to 10 Tb/s range. This paper discusses the requirements of optoelectronic devices operating in the femtosecond time domain and reviews recent progress of novel devices, such as femtosecond devices for ultrashort pulse generation, compression and switching.
{"title":"Femtosecond all-optical devices for tera-bit/sec optical networks","authors":"O. Wada","doi":"10.1109/IEDM.2000.904389","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904389","url":null,"abstract":"Ultrafast optoelectronic devices are crucial for fulfilling the future requirement of communication network throughput to enter the 1 Tb/s to 10 Tb/s range. This paper discusses the requirements of optoelectronic devices operating in the femtosecond time domain and reviews recent progress of novel devices, such as femtosecond devices for ultrashort pulse generation, compression and switching.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124733499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904378
A. Shanware, R. Khamankar, W. Mcpherson
The mixing of field-induced and current-induced degradation mechanisms can result in TDDB data showing a strong non-Arrhenius temperature dependence. Generally, at higher fields and lower temperatures, the current-induced mechanism dominates and a small activation energy is observed. At lower fields and higher temperatures, the field induced degradation mechanism tends to dominate and a strong temperature dependence is produced. The mixing of the current-induced and field-induced mechanisms can result in an activation energy associated with TDDB which is not unique but strongly dependent on test conditions and oxide thickness. The mixing is validated over various voltage, field, thickness and temperature regimes.
{"title":"Resolving the non-uniqueness of the activation energy associated with TDDB for SiO/sub 2/ thin films","authors":"A. Shanware, R. Khamankar, W. Mcpherson","doi":"10.1109/IEDM.2000.904378","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904378","url":null,"abstract":"The mixing of field-induced and current-induced degradation mechanisms can result in TDDB data showing a strong non-Arrhenius temperature dependence. Generally, at higher fields and lower temperatures, the current-induced mechanism dominates and a small activation energy is observed. At lower fields and higher temperatures, the field induced degradation mechanism tends to dominate and a strong temperature dependence is produced. The mixing of the current-induced and field-induced mechanisms can result in an activation energy associated with TDDB which is not unique but strongly dependent on test conditions and oxide thickness. The mixing is validated over various voltage, field, thickness and temperature regimes.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124995271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904395
K. Heeks, C. Towns, J. Burroughes, S. Ciná, A. Gunner
We report the latest developments in light emitting polymer (LEP) systems, including much improved blue device performance, developed at CDT. We also describe a high brightness, low voltage yellow system which is particularly suitable for use in passive matrix displays. Finally we describe materials improvements for red, green and blue which together with the co-development of a direct patterning technique, with the Seiko Epson Corporation, has lead to the production of a 16 grey-level full colour active matrix LED display.
{"title":"High performance light emitting polymers for colour displays","authors":"K. Heeks, C. Towns, J. Burroughes, S. Ciná, A. Gunner","doi":"10.1109/IEDM.2000.904395","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904395","url":null,"abstract":"We report the latest developments in light emitting polymer (LEP) systems, including much improved blue device performance, developed at CDT. We also describe a high brightness, low voltage yellow system which is particularly suitable for use in passive matrix displays. Finally we describe materials improvements for red, green and blue which together with the co-development of a direct patterning technique, with the Seiko Epson Corporation, has lead to the production of a 16 grey-level full colour active matrix LED display.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125360783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904367
M. Law, K. Jones
This paper introduces a new model for the {311} defect. The {311} defect is a key component of transient enhanced diffusion. This model is based on in-situ TEM annealing of defects. In-situ evidence suggests that there is no length dependence of the {311} defect evolution. Dissolution of the ensemble does, however, show a dependence on length since the defect loss rate is proportional to the number of defects. Defect nucleation is heterogeneous on clusters that result from the implant.
{"title":"A new model for {311} defects based on in situ measurements","authors":"M. Law, K. Jones","doi":"10.1109/IEDM.2000.904367","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904367","url":null,"abstract":"This paper introduces a new model for the {311} defect. The {311} defect is a key component of transient enhanced diffusion. This model is based on in-situ TEM annealing of defects. In-situ evidence suggests that there is no length dependence of the {311} defect evolution. Dissolution of the ensemble does, however, show a dependence on length since the defect loss rate is proportional to the number of defects. Defect nucleation is heterogeneous on clusters that result from the implant.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125578115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904403
S. Inumiya, Y. Morozumi, A. Yagishita, T. Saito, D. Gao, D. Choi, K. Hasebe, K. Suguro, Y. Tsunashima, T. Arikado
A conformable formation process of ultra-thin Ta/sub 2/O/sub 5/ gate dielectrics, which is applicable to 50 nm damascene gate MOSFETs, was developed. Assisted by H/sub 2/O, perfect conformability was successfully realized even in the narrow gate groove (50 nm), while maintaining a low gate leakage. An excellent device performance of S-factor 72 mV/decade was obtained in 90 nm MOSFET with amorphous Ta/sub 2/O/sub 5/ gate dielectrics of T/sub eff/ 1.6 nm.
{"title":"Conformable formation of high quality ultra-thin amorphous Ta/sub 2/O/sub 5/ gate dielectrics utilizing water assisted deposition (WAD) for sub 50 nm damascene metal gate MOSFETs","authors":"S. Inumiya, Y. Morozumi, A. Yagishita, T. Saito, D. Gao, D. Choi, K. Hasebe, K. Suguro, Y. Tsunashima, T. Arikado","doi":"10.1109/IEDM.2000.904403","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904403","url":null,"abstract":"A conformable formation process of ultra-thin Ta/sub 2/O/sub 5/ gate dielectrics, which is applicable to 50 nm damascene gate MOSFETs, was developed. Assisted by H/sub 2/O, perfect conformability was successfully realized even in the narrow gate groove (50 nm), while maintaining a low gate leakage. An excellent device performance of S-factor 72 mV/decade was obtained in 90 nm MOSFET with amorphous Ta/sub 2/O/sub 5/ gate dielectrics of T/sub eff/ 1.6 nm.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125594163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904247
S. Nakamura
Solid-state lighting is based on short wavelength nitride-based light emitting diodes (LEDs) or laser diodes (LDs), that can produce white light. Presently, nitride-based LEDs have efficiencies exceeding those of incandescent light bulbs and most likely, will surpass those of fluorescent lights in the near future. In this talk, the latest performance of nitride-based ultraviolet (UV)/blue/green/amber/white LEDs and violet/blue LDs will be discussed.
{"title":"III-V nitride-based LEDs and lasers: Current status and future opportunities","authors":"S. Nakamura","doi":"10.1109/IEDM.2000.904247","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904247","url":null,"abstract":"Solid-state lighting is based on short wavelength nitride-based light emitting diodes (LEDs) or laser diodes (LDs), that can produce white light. Presently, nitride-based LEDs have efficiencies exceeding those of incandescent light bulbs and most likely, will surpass those of fluorescent lights in the near future. In this talk, the latest performance of nitride-based ultraviolet (UV)/blue/green/amber/white LEDs and violet/blue LDs will be discussed.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128343826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904369
A. Shima, T. Jinbo, J. Ushio, J. Oh, K. Ono, M. Oshima, N. Natsuaki
We have quantitatively investigated how boron segregates to regions dose to the surface, and what controls this phenomenon, using XPS and Backside SIMS measurement techniques. We found that, on the contrary to the equilibrium segregation, the pileup of boron are mainly on and within 0.6 nm of the Si side of the interface, and that there is no difference between the kind of encapsulation. This also suggests that the pileup of boron is mainly on the Si side, and implies that the main factor in this segregation is the existence of the Si surface. From the viewpoint of device fabrication, this result seems to be useful in terms of the fabrication of side-walls. The possibility for boron pileup to occur in the interstitial state was also shown.
{"title":"Investigation of a model for the segregation and pile-up of boron at the SiO/sub 2//Si interface during the formation of ultrashallow p/sup +/ junctions","authors":"A. Shima, T. Jinbo, J. Ushio, J. Oh, K. Ono, M. Oshima, N. Natsuaki","doi":"10.1109/IEDM.2000.904369","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904369","url":null,"abstract":"We have quantitatively investigated how boron segregates to regions dose to the surface, and what controls this phenomenon, using XPS and Backside SIMS measurement techniques. We found that, on the contrary to the equilibrium segregation, the pileup of boron are mainly on and within 0.6 nm of the Si side of the interface, and that there is no difference between the kind of encapsulation. This also suggests that the pileup of boron is mainly on the Si side, and implies that the main factor in this segregation is the existence of the Si surface. From the viewpoint of device fabrication, this result seems to be useful in terms of the fabrication of side-walls. The possibility for boron pileup to occur in the interstitial state was also shown.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128366414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-10DOI: 10.1109/IEDM.2000.904327
C. Radens, S. Kudelka, L. Nesbit, R. Malik, T. Dyer, C. Dubuc, T. Joseph, M. Seitz, L. Clevenger, N. Arnold, J. Mandelman, R. Divakaruni, D. Casarotto, D. Lea, V. C. Jaiprakash, J. Sim, J. Faltermeier, K. Low, J. Strane, S. Halle, Q. Ye, S. Bukofsky, U. Gruening, T. Schloesser, G. Bronner
This paper describes a novel 6F/sup 2/ trench-capacitor DRAM with a trench-sidewall vertical-channel array transistor. The cell features a line/space pattern for the active area, single-sided buried-strap node contact, vertical transistor channel formed along the upper region of the trench capacitor, a device active area bounded by the isolation trench and capacitor collar, and a single bit contact per cell.
{"title":"An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM","authors":"C. Radens, S. Kudelka, L. Nesbit, R. Malik, T. Dyer, C. Dubuc, T. Joseph, M. Seitz, L. Clevenger, N. Arnold, J. Mandelman, R. Divakaruni, D. Casarotto, D. Lea, V. C. Jaiprakash, J. Sim, J. Faltermeier, K. Low, J. Strane, S. Halle, Q. Ye, S. Bukofsky, U. Gruening, T. Schloesser, G. Bronner","doi":"10.1109/IEDM.2000.904327","DOIUrl":"https://doi.org/10.1109/IEDM.2000.904327","url":null,"abstract":"This paper describes a novel 6F/sup 2/ trench-capacitor DRAM with a trench-sidewall vertical-channel array transistor. The cell features a line/space pattern for the active area, single-sided buried-strap node contact, vertical transistor channel formed along the upper region of the trench capacitor, a device active area bounded by the isolation trench and capacitor collar, and a single bit contact per cell.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114222151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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