An FPGA-based re-configurable functional tester for memory chips

Abstract

The paper presents a prototype re-configurable tester for memory chips. The new tester consists of a memory test-circuitry compiler, a synthesis/mapping CAD tool, and an FPGA-based re-configurable hardware platform. The compiler makes user-specified parameters of memory under test (such as the address and data bus widths, the march test and the background data) as input and generates the test circuitry required to functionally, test the target memory chips. This framework not only enables the automatic synthesis/mapping of the test circuitry into the re-configurable hardware platform, it also guarantees that the hardware platform can correctly operate at the desired clock rate for the user specified parameters. The proposed solution can reduce the memory tester cost by providing hardware re-configurability to support a wide range of memory chips. We demonstrate that the prototype tester can be automatically configured to test SDRAM chips above 100 MHz.