Abstract only given, substantially as follows. These are exciting times for digital technology, as we see continual reductions in feature size and power supply voltage, and increases in chip size, density and speed. Unfortunately, test costs seem to demand an increasing fraction of the total production costs. The author discusses the relationship between industry and academic research from the perspective of funding, sharing of data and distribution of software.
{"title":"Challenges for the academic test community","authors":"M. Breuer, K. Cheng","doi":"10.1109/ATS.2000.10004","DOIUrl":"https://doi.org/10.1109/ATS.2000.10004","url":null,"abstract":"Abstract only given, substantially as follows. These are exciting times for digital technology, as we see continual reductions in feature size and power supply voltage, and increases in chip size, density and speed. Unfortunately, test costs seem to demand an increasing fraction of the total production costs. The author discusses the relationship between industry and academic research from the perspective of funding, sharing of data and distribution of software.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115472904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the last two decades of the 20th century, the integrated circuit (IC) industry has prolonged and redefined Taiwan Economic Miracle. The relay has passed from OEM to IDM then to the foundry services. With the strong supports from the foundry and manufacturing sectors, the energetic and creative design sector has seen an unsurpassed opportunity in the new Millennium. The design sector will continue the trend and create a new horizon. The shift in the paradigm will have a significant impact on the test sector. In the Taiwan Test Industry Session, we will discuss how the test sector shall react, what the emerging technologies are, and what the new business protocol should be. We have invited distinguished members from designer, test, and ATE sectors to express their inside views. f The experts from design sectors will present their problems and requirements in the deep sub-micron circuit testing. The expert from the test sectors will present their current capability and technology roadmap regarding the technical concerns. Finally, ATE venders will showcase their advanced machine in the New Millennium to tackle the problems. Technology wise, the testing of System on Chip, System in Package, mixed signal, RF, and signal integrity are some of the issues that will be discussed. Infrastructure wise, the protocol for the technical cooperation on the test development in the circuit design stage and the model for the business operation in the final test stage are the focus of the presentations.
{"title":"Taiwan test industry session: value added testing in the new millennium","authors":"Chung-Len Lee","doi":"10.1109/ATS.2000.893594","DOIUrl":"https://doi.org/10.1109/ATS.2000.893594","url":null,"abstract":"In the last two decades of the 20th century, the integrated circuit (IC) industry has prolonged and redefined Taiwan Economic Miracle. The relay has passed from OEM to IDM then to the foundry services. With the strong supports from the foundry and manufacturing sectors, the energetic and creative design sector has seen an unsurpassed opportunity in the new Millennium. The design sector will continue the trend and create a new horizon. The shift in the paradigm will have a significant impact on the test sector. In the Taiwan Test Industry Session, we will discuss how the test sector shall react, what the emerging technologies are, and what the new business protocol should be. We have invited distinguished members from designer, test, and ATE sectors to express their inside views. f The experts from design sectors will present their problems and requirements in the deep sub-micron circuit testing. The expert from the test sectors will present their current capability and technology roadmap regarding the technical concerns. Finally, ATE venders will showcase their advanced machine in the New Millennium to tackle the problems. Technology wise, the testing of System on Chip, System in Package, mixed signal, RF, and signal integrity are some of the issues that will be discussed. Infrastructure wise, the protocol for the technical cooperation on the test development in the circuit design stage and the model for the business operation in the final test stage are the focus of the presentations.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124393606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High operation frequency and strict timing behavior are characteristics of modern high performance integrated circuits, which require a digital system simulator to accurately simulate not only the logic function but also the timing behavior of a circuit. This paper presents some experimental results by SPICE to validate the analytical approach of Boolean process, and extract some data for a numerical waveform simulation. The paper also presents a waveform simulator and its results of experiments, which is very different from traditional logic simulator.
{"title":"A waveform simulator based on Boolean process","authors":"Lijian Li, Xiaoyang Yu, Cheng-Wen Wu, Y. Min","doi":"10.1109/ATS.2000.893617","DOIUrl":"https://doi.org/10.1109/ATS.2000.893617","url":null,"abstract":"High operation frequency and strict timing behavior are characteristics of modern high performance integrated circuits, which require a digital system simulator to accurately simulate not only the logic function but also the timing behavior of a circuit. This paper presents some experimental results by SPICE to validate the analytical approach of Boolean process, and extract some data for a numerical waveform simulation. The paper also presents a waveform simulator and its results of experiments, which is very different from traditional logic simulator.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"108 2-3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120895126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A Built-In Self-Test (BIST) methodology and a test pattern generation (TPG) architecture for testing static random access memory (SRAM) interconnect at board level via IEEE 1149.1 Boundary Scan (BS) Architecture are presented. Due to the expense and complexity of BS circuitry the widely-used SRAMs on most modern telecommunication circuit boards seldom contain BS architecture. (We call such non-boundary scan ICs cluster-ICs.) Hence, a methodology that tests the large numbers of board-level interconnects at the control, address, and data lines of cluster SRAMs is necessary. This is especially essential for board-level interconnect BIST which is used not only for manufacturing testing but also for system testing after integration. Newly identified prohibited conditions, which enable re-arrangement and merger of tests, are incorporated into test conditions for SRAM cluster interconnects. These improvements have been exploited to develop an efficient test procedure that is suitable for BIST. The proposed BIST methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable SRAM cluster interconnect faults, (iii) have low area overhead, and (iv) have short test lengths.
{"title":"BIST TPG for SRAM cluster interconnect testing at board level","authors":"Chen-Huan Chiang, S. Gupta","doi":"10.1109/ATS.2000.893603","DOIUrl":"https://doi.org/10.1109/ATS.2000.893603","url":null,"abstract":"A Built-In Self-Test (BIST) methodology and a test pattern generation (TPG) architecture for testing static random access memory (SRAM) interconnect at board level via IEEE 1149.1 Boundary Scan (BS) Architecture are presented. Due to the expense and complexity of BS circuitry the widely-used SRAMs on most modern telecommunication circuit boards seldom contain BS architecture. (We call such non-boundary scan ICs cluster-ICs.) Hence, a methodology that tests the large numbers of board-level interconnects at the control, address, and data lines of cluster SRAMs is necessary. This is especially essential for board-level interconnect BIST which is used not only for manufacturing testing but also for system testing after integration. Newly identified prohibited conditions, which enable re-arrangement and merger of tests, are incorporated into test conditions for SRAM cluster interconnects. These improvements have been exploited to develop an efficient test procedure that is suitable for BIST. The proposed BIST methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable SRAM cluster interconnect faults, (iii) have low area overhead, and (iv) have short test lengths.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127251089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The use of embedded cores poses several new problems in testing systems built around them. An important one amongst them is the need to achieve high fault coverage in an embedded context. Several impediments exist to obtaining a high fault coverage in such embedded systems. This paper presents a set of techniques for enhancing the fault coverage in an embedded DSP core based system. Its main contributions are: (i) examines the various test constraints in such a system and the impediments to achieving a high fault coverage therein; (ii) presents the development of functional testing techniques to enhance the coverage of the individual components; (iii) complements this effort by presenting fault analysis techniques, to further enhance this coverage. The techniques described in the paper have been used to improve the fault coverage of devices built around Texas Instruments new DSP core, TMS320C27xx. Results indicate the effectiveness of functional testing and fault analysis techniques in raising the DSP core and memory wrapper logic coverage above 95%, over and above the best results obtained through ATPG.
{"title":"Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems","authors":"Ameet Bagwe, R. Parekhji","doi":"10.1109/ATS.2000.893635","DOIUrl":"https://doi.org/10.1109/ATS.2000.893635","url":null,"abstract":"The use of embedded cores poses several new problems in testing systems built around them. An important one amongst them is the need to achieve high fault coverage in an embedded context. Several impediments exist to obtaining a high fault coverage in such embedded systems. This paper presents a set of techniques for enhancing the fault coverage in an embedded DSP core based system. Its main contributions are: (i) examines the various test constraints in such a system and the impediments to achieving a high fault coverage therein; (ii) presents the development of functional testing techniques to enhance the coverage of the individual components; (iii) complements this effort by presenting fault analysis techniques, to further enhance this coverage. The techniques described in the paper have been used to improve the fault coverage of devices built around Texas Instruments new DSP core, TMS320C27xx. Results indicate the effectiveness of functional testing and fault analysis techniques in raising the DSP core and memory wrapper logic coverage above 95%, over and above the best results obtained through ATPG.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123261316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Hashizume, H. Yotsuyanagi, M. Ichimiya, T. Tamesada, M. Takeda
A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.
{"title":"High speed IDDQ test and its testability for process variation","authors":"M. Hashizume, H. Yotsuyanagi, M. Ichimiya, T. Tamesada, M. Takeda","doi":"10.1109/ATS.2000.893647","DOIUrl":"https://doi.org/10.1109/ATS.2000.893647","url":null,"abstract":"A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123297496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Valentin Muresan, Xiaojun Wang, Valentin Muresan, M. Vladutiu
A distribution-graph based scheduling algorithm is proposed together with an extended tree growing technique to deal with the problem of unequal-length block-test scheduling under power dissipation constraints. The extended tree growing technique is used in combination with the classical scheduling approach in order to improve the test concurrency having assigned power dissipation limits. Its goal is to achieve a balanced test power dissipation by employing a least mean square error function. The least mean square error function is a distribution-graph based global priority function. Test scheduling examples and experiments highlight in the end the efficiency of this approach towards a system-level test scheduling algorithm.
{"title":"Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling","authors":"Valentin Muresan, Xiaojun Wang, Valentin Muresan, M. Vladutiu","doi":"10.1109/ATS.2000.893668","DOIUrl":"https://doi.org/10.1109/ATS.2000.893668","url":null,"abstract":"A distribution-graph based scheduling algorithm is proposed together with an extended tree growing technique to deal with the problem of unequal-length block-test scheduling under power dissipation constraints. The extended tree growing technique is used in combination with the classical scheduling approach in order to improve the test concurrency having assigned power dissipation limits. Its goal is to achieve a balanced test power dissipation by employing a least mean square error function. The least mean square error function is a distribution-graph based global priority function. Test scheduling examples and experiments highlight in the end the efficiency of this approach towards a system-level test scheduling algorithm.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114033927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Presents an approach for fault detection in programmable wiring networks (PWNs). A comprehensive fault model which includes faults in the nets (open, stuck-at and shorts) as well as in the switches (stuck-off, stuck-on and programming faults) is assumed at both the physical and behavioral levels. In a PWN, the most important issue is to find the minimal number of configurations (or programming phases) as the dominant figure of merit of testing. Through the construction of different graphs, it is shown that this process corresponds to finding the node-disjoint path-sets such that each switch is turned on/off at least once and adjacencies in the nets for possible bridge faults (shorts) are verified. To account for 100% fault coverage of bridge faults, a post-processing algorithm may be required.
{"title":"Testing programmable interconnect systems: an algorithmic approach","authors":"Bin Liu, F. Lombardi, Wei-Kang Huang","doi":"10.1109/ATS.2000.893642","DOIUrl":"https://doi.org/10.1109/ATS.2000.893642","url":null,"abstract":"Presents an approach for fault detection in programmable wiring networks (PWNs). A comprehensive fault model which includes faults in the nets (open, stuck-at and shorts) as well as in the switches (stuck-off, stuck-on and programming faults) is assumed at both the physical and behavioral levels. In a PWN, the most important issue is to find the minimal number of configurations (or programming phases) as the dominant figure of merit of testing. Through the construction of different graphs, it is shown that this process corresponds to finding the node-disjoint path-sets such that each switch is turned on/off at least once and adjacencies in the nets for possible bridge faults (shorts) are verified. To account for 100% fault coverage of bridge faults, a post-processing algorithm may be required.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130632545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The use of analog VLSI technology on ordinary but complex electronic products has in the test one of its last frontiers. The design for testability paradigm should allow the test plan implementation early in the design cycle. However, in a successful test strategy, fault simulation should be carried out in order to evaluate appropriate test patterns, fault grade, etc. This way adequate fault models must be established. This paper shows the suitability and the straightforward consequences on testing of complex analog circuits when using OpAmp functional fault macromodels. Due to the lack of fault models, suitable for operational amplifiers fault simulation, we propose methodology for functional fault modeling and a method for test pattern generation. A fault dictionary for OpAmps is built and a procedure for compact test vector construction is proposed. The method is used to detect OpAmp faults in a pulse width modulator. The obtained results show that the proposed method is able to verify high level OpAmp requirements, such as open loop gain, slew-rate and CMMR, with good compromise between fault modeling and the analog circuit simulation complexity.
{"title":"Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers","authors":"J. Calvano, V. Alves, M. Lubaszewski","doi":"10.1109/ATS.2000.893609","DOIUrl":"https://doi.org/10.1109/ATS.2000.893609","url":null,"abstract":"The use of analog VLSI technology on ordinary but complex electronic products has in the test one of its last frontiers. The design for testability paradigm should allow the test plan implementation early in the design cycle. However, in a successful test strategy, fault simulation should be carried out in order to evaluate appropriate test patterns, fault grade, etc. This way adequate fault models must be established. This paper shows the suitability and the straightforward consequences on testing of complex analog circuits when using OpAmp functional fault macromodels. Due to the lack of fault models, suitable for operational amplifiers fault simulation, we propose methodology for functional fault modeling and a method for test pattern generation. A fault dictionary for OpAmps is built and a procedure for compact test vector construction is proposed. The method is used to detect OpAmp faults in a pulse width modulator. The obtained results show that the proposed method is able to verify high level OpAmp requirements, such as open loop gain, slew-rate and CMMR, with good compromise between fault modeling and the analog circuit simulation complexity.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121380382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present a framework that enables the computation of tight ranges of signal arrival, transition, and required times for rising and falling transitions at each circuit line, given an input sequence consisting of two partially specified vectors. At one extreme, when the vectors are completely unspecified, this framework becomes identical to static timing analysis (STA). At the other extreme, when the vectors are completely specified, this framework performs timing simulation (TS). Our key motivation for developing this framework was to reduce the amount of search required by a test generator that uses timing information. During test generation for a target fault, values are specified incrementally and this framework enables refinement of timing windows. We demonstrate that this approach significantly improves test generation efficiency. In this mode, the ATPG is said to be performing incremental timing refinement (ITR).
{"title":"A new framework for static timing analysis, incremental timing refinement, and timing simulation","authors":"Liang-Chi Chen, S. Gupta, M. Breuer","doi":"10.1109/ATS.2000.893610","DOIUrl":"https://doi.org/10.1109/ATS.2000.893610","url":null,"abstract":"In this paper we present a framework that enables the computation of tight ranges of signal arrival, transition, and required times for rising and falling transitions at each circuit line, given an input sequence consisting of two partially specified vectors. At one extreme, when the vectors are completely unspecified, this framework becomes identical to static timing analysis (STA). At the other extreme, when the vectors are completely specified, this framework performs timing simulation (TS). Our key motivation for developing this framework was to reduce the amount of search required by a test generator that uses timing information. During test generation for a target fault, values are specified incrementally and this framework enables refinement of timing windows. We demonstrate that this approach significantly improves test generation efficiency. In this mode, the ATPG is said to be performing incremental timing refinement (ITR).","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121458761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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