A Mechanism for Adjustable-Delay-Buffer Selection to Dynamically Control Clock Skew

Abstract

Clock skew minimization is a very important task for sequential timing optimization. As the technology node continues to shrink, the clock skew caused by the effects of process/voltage/temperature (PVT) variations may result in a serious problem. To deal with this problem, the previous work proposed a self-adjusting mechanism to dynamically control the clock skew. However, the previous work requires a lot of clock buffers for dynamic clock skew control. In this paper, we present a new mechanism for the selection of the channels of adjustable-delay-buffers (ADBs). Based on the proposed new mechanism, a lot of clock buffers in the ADBs can be saved. Experimental results consistently show that our approach works well in practice.