Janine Chen, B. Bolin, Li-C. Wang, Jing Zeng, D. Drmanac, Michael Mateja
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引用次数: 14
Abstract
Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related knowledge that would be difficult to find otherwise.
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