Area Constraint Aware Physical Unclonable Function for Intelligence Module

Y. Nozaki, M. Yoshikawa
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引用次数: 3

Abstract

Artificial intelligence technology such as neural network (NN) is widely used in intelligence module for Internet of Things (IoT). On the other hand, the risk of illegal attacks for IoT devices is pointed out; therefore, security countermeasures such as an authentication are very important. In the field of hardware security, the physical unclonable functions (PUFs) have been attracted attention as authentication techniques to prevent the semiconductor counterfeits. However, implementation of the dedicated hardware for both of NN and PUF increases circuit area. Therefore, this study proposes a new area constraint aware PUF for intelligence module. The proposed PUF utilizes the propagation delay time from input layer to output layer of NN. To share component for operation, the proposed PUF reduces the circuit area. Experiments using a field programmable gate array evaluate circuit area and PUF performance. In the result of circuit area, the proposed PUF was smaller than the conventional PUFs was showed. Then, in the PUF performance evaluation, for steadiness, diffuseness, and uniqueness, favorable results were obtained.
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智能模块的区域约束感知物理不可克隆功能
神经网络(NN)等人工智能技术被广泛应用于物联网智能模块中。另一方面,指出了物联网设备遭受非法攻击的风险;因此,认证等安全对策非常重要。在硬件安全领域,物理不可克隆功能(PUFs)作为防止半导体仿冒品的认证技术受到了广泛的关注。然而,对于神经网络和PUF的专用硬件的实现增加了电路面积。因此,本研究提出了一种新的智能模块区域约束感知PUF。所提出的PUF利用了神经网络从输入层到输出层的传播延迟时间。为了实现元器件共享,PUF减小了电路的面积。实验使用现场可编程门阵列评估电路面积和PUF性能。电路面积结果表明,所提出的PUF比传统的PUF要小。在PUF性能评价中,从稳定性、弥漫性、唯一性三个方面进行了较好的评价。
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