Jatin N. Mistry, J. Biggs, James Myers, B. Al-Hashimi, D. Flynn
{"title":"dRail: A Novel Physical Layout Methodology for Power Gated Circuits","authors":"Jatin N. Mistry, J. Biggs, James Myers, B. Al-Hashimi, D. Flynn","doi":"10.1007/978-3-642-36157-9_25","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Workshop on Power and Timing Modeling, Optimization and Simulation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-3-642-36157-9_25","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}