LDO with a Dual Complementary Buffer Architecture

Abstract

This paper presents a 5V LDO architecture with a buffered error amplifier. This is achieved by using a functional block called a dual complementary buffer which consists of two buffers, one using a NMOS output transistor, the other a PMOS output transistor. The main advantage of this architecture is the rail-to-rail output voltage swing of the buffer, improving performance in both the tracking and the regulating operating regions of the voltage regulator. Simulation results show load regulation of 4.47uV/mA and line regulation of 3.92uV/v. The maximum input voltage is 40V and the maximum load current is 200mA. The LDO was simulated using a 0.8um BiCMOS process.