Factors influencing the formation of voids in chip component solder joints

2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2013-10-01 DOI:10.1109/SIITME.2013.6743690

M. Pantazica, P. Svasta, H. Wohlrabe, K. Wolter

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引用次数: 5

Abstract

The aim of this paper is to present the most recent results obtained after conducting a complex experiment designed with the help of the Design of Experiments (DoE) method. The purpose of this experiment is to evaluate the dependencies between the layout design and the production quality of surface mount boards. The last part of this experiment is focused on studying the effects of solder voids on the reliability of solder joints. Solder joints are investigated and evaluated with the help of an X-Ray equipment. Based on the X-Ray images, the void area in a solder joint is measured (in pixels). The statistical analysis has revealed that all factors considered to have an influence on the void formation in this experiment are significant. Moreover all the interactions between these factors are statistically significant. The largest void content is obtained in case of microMELF components, chemSn surface finish and solder paste type C. As opposed to our expectations, the void area is the smallest in case of Vapour Phase Soldering.

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影响芯片元件焊点空隙形成的因素

本文的目的是介绍利用实验设计(DoE)方法进行复杂实验后获得的最新结果。本实验的目的是评估布局设计与表面贴装板的生产质量之间的依赖关系。实验的最后一部分重点研究了焊点空隙对焊点可靠性的影响。在x射线设备的帮助下，对焊点进行调查和评估。根据x射线图像，测量焊点的空洞面积(以像素为单位)。统计分析表明，本实验中考虑的影响孔隙形成的所有因素都是显著的。各因素之间的相互作用均具有统计学显著性。在微型melf元件、化学锡表面光面和c型锡膏的情况下，获得的空洞含量最大。与我们的预期相反，在气相焊接的情况下，空洞面积最小。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)

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