A 47ns 64KW × 4b CMOS DRAM with relaxed timing requirements

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156944

T. Kobayashi, K. Arimoto, Y. Ikeda, M. Hatanaka, K. Mashiko, M. Yamada

引用次数: 1

Abstract

A 256Kb DRAM which eliminates the positive-going RAS signal edge from the internal timing by a time-out function, will be reported. The access time is 47ns with predecoding, and power dissipation is 115mW at 200ns cycle time.

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一个47ns 64KW × 4b CMOS DRAM与宽松的时序要求

将报道一种256Kb的DRAM，它通过超时功能从内部定时中消除正向RAS信号边缘。前置电路的接入时间为47ns, 200ns周期时的功耗为115mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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