{"title":"The AMULET2e cache system","authors":"J. Garside, S. Temple, R. Mehra","doi":"10.1109/ASYNC.1996.494452","DOIUrl":null,"url":null,"abstract":"AMULET2e is an asynchronous microprocessor system based on the AMULET2 processor core. In addition to the processor it incorporates a number of distinct subsystems, the most notable of which is an asynchronous on-chip cache. This includes several novel features which exploit the asynchronous design style to increase throughput and reduce power consumption. These features are evident at a number of levels in the design. For example, the cache is micropipelined to increase its throughput, at the architectural level there is an arbitration free non-blocking line fetch mechanism while at the circuit design level there is a power-saving RAM sense amplifier control circuit. A significant property of the cache system is its ability to cycle in a data dependent way which allows the system to approach average case performance.","PeriodicalId":365358,"journal":{"name":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"280 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.1996.494452","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 27

Abstract

AMULET2e is an asynchronous microprocessor system based on the AMULET2 processor core. In addition to the processor it incorporates a number of distinct subsystems, the most notable of which is an asynchronous on-chip cache. This includes several novel features which exploit the asynchronous design style to increase throughput and reduce power consumption. These features are evident at a number of levels in the design. For example, the cache is micropipelined to increase its throughput, at the architectural level there is an arbitration free non-blocking line fetch mechanism while at the circuit design level there is a power-saving RAM sense amplifier control circuit. A significant property of the cache system is its ability to cycle in a data dependent way which allows the system to approach average case performance.
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AMULET2e缓存系统
AMULET2e是基于AMULET2处理器内核的异步微处理器系统。除了处理器之外,它还集成了许多不同的子系统,其中最引人注目的是异步片上缓存。这包括几个利用异步设计风格来提高吞吐量和降低功耗的新特性。这些特性在设计的许多层面上都很明显。例如,高速缓存是微流水线的,以增加其吞吐量,在架构层面上有一个仲裁无阻塞的线路提取机制,而在电路设计层面上有一个省电的RAM感测放大器控制电路。缓存系统的一个重要特性是以数据依赖的方式进行循环的能力,这使得系统能够接近平均情况的性能。
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