{"title":"CMOS continuous-time CMFB circuit with improved linearity","authors":"J. M. Carrillo, J. L. Ausín, J. F. Duque-Carrillo","doi":"10.1109/ECCTD.2007.4529531","DOIUrl":null,"url":null,"abstract":"A continuous-time common-mode feedback (CMFB) network consisting of two unity-gain buffers and two passive resistors is introduced in this paper. According to the comparison with a previous implementation, the common-mode control structure presented shows an improved linearity performance as well as a higher immunity to device mismatches. The CMFB circuit has been included in the design of a fully differential voltage buffer, based on a fully differential difference amplifier. Simulated results, obtained in a 0.35-mum standard CMOS technology, are provided in order to show the performance of the proposed approach.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"318 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 18th European Conference on Circuit Theory and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2007.4529531","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A continuous-time common-mode feedback (CMFB) network consisting of two unity-gain buffers and two passive resistors is introduced in this paper. According to the comparison with a previous implementation, the common-mode control structure presented shows an improved linearity performance as well as a higher immunity to device mismatches. The CMFB circuit has been included in the design of a fully differential voltage buffer, based on a fully differential difference amplifier. Simulated results, obtained in a 0.35-mum standard CMOS technology, are provided in order to show the performance of the proposed approach.