Pub Date : 2007-08-26DOI: 10.1109/ECCTD.2007.4529569
Phuoc Vo Tan, G. Millérioux, J. Daafouz
It is widely admitted that most of chaotic cryptosystems belong to the class of symmetric key ciphers but few of them have really been compared with standard existing ones. As a consequence, their design often resorts to empirical approaches with trial-and-error settings. This paper must be considered as an attempt to handle such a situation. An in-depth comparison between a fully-fledged self-synchronous stream cipher called Mosquito and one of the most promising chaotic cryptosystem, namely hybrid message-embedding, is carried out. It is given a correspondence between the design parameters involved in the two respective schemes, in particular the size of the secret key, the required memory, the dimension of the system. Furthermore, we put a special emphasis on the link between the notion of relative degree of a dynamical system and the concept of pipelining.
{"title":"A comparison between the message embedded cryptosystem and the self-synchronous stream cipher Mosquito","authors":"Phuoc Vo Tan, G. Millérioux, J. Daafouz","doi":"10.1109/ECCTD.2007.4529569","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529569","url":null,"abstract":"It is widely admitted that most of chaotic cryptosystems belong to the class of symmetric key ciphers but few of them have really been compared with standard existing ones. As a consequence, their design often resorts to empirical approaches with trial-and-error settings. This paper must be considered as an attempt to handle such a situation. An in-depth comparison between a fully-fledged self-synchronous stream cipher called Mosquito and one of the most promising chaotic cryptosystem, namely hybrid message-embedding, is carried out. It is given a correspondence between the design parameters involved in the two respective schemes, in particular the size of the secret key, the required memory, the dimension of the system. Furthermore, we put a special emphasis on the link between the notion of relative degree of a dynamical system and the concept of pipelining.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126458432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529702
Yaohui Kong, Shuzheng Xu, Huazhong Yang
The paper presents a highly linear CMOS triode transconductor with a wide tuning capability for low voltage and low power applications. The use of a novel feedback loop regulating the drain voltage of input transistor in triode region achieves a highly linear voltage to current conversion. This design uses UMC 0.18 um CMOS process. Simulation result shows the proposed transconductor, operated in 1.2 V supply voltage, has less than 0.1% total harmonic distortions (THD) for 1 MHz 0.8 Vp-p differential input. The power consumption is 203 uW, when 0.55 V control voltage is applied.
本文介绍了一种具有宽调谐能力的高线性CMOS三极管，适用于低电压和低功耗应用。利用一种新颖的反馈回路调节三极管区输入晶体管的漏极电压，实现了高线性电压-电流转换。本设计采用UMC 0.18 um CMOS工艺。仿真结果表明，在1.2 V电源电压下，在1 MHz 0.8 Vp-p差分输入下，该晶体管的总谐波畸变小于0.1%。当施加0.55 V控制电压时，功耗为203 uW。
{"title":"A highly linear low voltage CMOS triode transconductor","authors":"Yaohui Kong, Shuzheng Xu, Huazhong Yang","doi":"10.1109/ECCTD.2007.4529702","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529702","url":null,"abstract":"The paper presents a highly linear CMOS triode transconductor with a wide tuning capability for low voltage and low power applications. The use of a novel feedback loop regulating the drain voltage of input transistor in triode region achieves a highly linear voltage to current conversion. This design uses UMC 0.18 um CMOS process. Simulation result shows the proposed transconductor, operated in 1.2 V supply voltage, has less than 0.1% total harmonic distortions (THD) for 1 MHz 0.8 Vp-p differential input. The power consumption is 203 uW, when 0.55 V control voltage is applied.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116759432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529688
K. Hayashi, T. Katao, H. Fujisaka, T. Kamio, K. Haeiwa
This paper describes piecewise linear circuits operating directly on first-order multi-level and second-order binary sigma-delta modulated signals. The sigma-delta modulated signal sequences contain subsequences which reflect whether the inputs to sigma-delta modulators are positive or negative. We build circuits performing absolute operation with detectors of the subsequences. Using the absolute circuits, we build various piece- wise linear circuits, such as Min/Max circuits. These piecewise linear circuits can be built of a smaller number of logic gates and perform more precise piecewise linear operation at a high oversampling ratio than multi-bit Nyquist rate circuits.
{"title":"Piecewise linear circuits operating on first-order multi-level and second-order binary sigma-delta modulated signals","authors":"K. Hayashi, T. Katao, H. Fujisaka, T. Kamio, K. Haeiwa","doi":"10.1109/ECCTD.2007.4529688","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529688","url":null,"abstract":"This paper describes piecewise linear circuits operating directly on first-order multi-level and second-order binary sigma-delta modulated signals. The sigma-delta modulated signal sequences contain subsequences which reflect whether the inputs to sigma-delta modulators are positive or negative. We build circuits performing absolute operation with detectors of the subsequences. Using the absolute circuits, we build various piece- wise linear circuits, such as Min/Max circuits. These piecewise linear circuits can be built of a smaller number of logic gates and perform more precise piecewise linear operation at a high oversampling ratio than multi-bit Nyquist rate circuits.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"6 28","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120930194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529544
V. Brea, M. Laiho, Natalia A. Fernandez-Garcia, A. Paasio, D. Cabello
This paper examines three apparently different computing models, namely, threshold logic (TL), cellular nonlinear networks (CNN) and single instruction multiple data (SIMD). TL is an area of interest in modern VLSI design and computational neuroscience. CNNs are mainly employed in image processing. Conventional SIMD architectures aim at exploiting data parallelism to speed up the execution time of computation intensive algorithms. The scope of this paper is limited to the processing of binary images. Within this scope, the paper conveys three main conclusions. First, the three computing models can be used for binary image processing. Second, not only 2D-CNNs are a sub-class of SIMD architectures, but also synchronous 2D- CNNs with a reduced set of coefficient circuits act as a classical 1-bit SIMD processing element with NEWS (North-East-West- South) for nearest-neighbor communications. Third, TL gates (TLGs) are proved to be an alternative to implement binary 2D- CNNs, leading to on-chip solutions with a very high performance.
{"title":"Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data computing models","authors":"V. Brea, M. Laiho, Natalia A. Fernandez-Garcia, A. Paasio, D. Cabello","doi":"10.1109/ECCTD.2007.4529544","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529544","url":null,"abstract":"This paper examines three apparently different computing models, namely, threshold logic (TL), cellular nonlinear networks (CNN) and single instruction multiple data (SIMD). TL is an area of interest in modern VLSI design and computational neuroscience. CNNs are mainly employed in image processing. Conventional SIMD architectures aim at exploiting data parallelism to speed up the execution time of computation intensive algorithms. The scope of this paper is limited to the processing of binary images. Within this scope, the paper conveys three main conclusions. First, the three computing models can be used for binary image processing. Second, not only 2D-CNNs are a sub-class of SIMD architectures, but also synchronous 2D- CNNs with a reduced set of coefficient circuits act as a classical 1-bit SIMD processing element with NEWS (North-East-West- South) for nearest-neighbor communications. Third, TL gates (TLGs) are proved to be an alternative to implement binary 2D- CNNs, leading to on-chip solutions with a very high performance.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127066536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529631
F. Centurelli, A. Simonetti, A. Trifiletti
A high-performance sample-and-hold (S/H) front end is proposed. In the double-buffered S/H circuit, the standard voltage follower based on a high-gain two-stage opamp is replaced with a couple of low gain amplifiers in feedback mode. Simulation results show that the proposed active-feedback voltage follower allows a very low gain error with low sensitivity to circuit mismatches and a limited distortion penalty. This makes it suitable to be used in time interleaving applications with distributed sampling.
{"title":"A sample-and-hold circuit with very low gain error for time interleaving applications","authors":"F. Centurelli, A. Simonetti, A. Trifiletti","doi":"10.1109/ECCTD.2007.4529631","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529631","url":null,"abstract":"A high-performance sample-and-hold (S/H) front end is proposed. In the double-buffered S/H circuit, the standard voltage follower based on a high-gain two-stage opamp is replaced with a couple of low gain amplifiers in feedback mode. Simulation results show that the proposed active-feedback voltage follower allows a very low gain error with low sensitivity to circuit mismatches and a limited distortion penalty. This makes it suitable to be used in time interleaving applications with distributed sampling.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124846013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529766
A. Buonomo, A. L. Schiavo
A nonlinear perturbation model of a complementary LC-tuned voltage controlled oscillator is derived, which consists of two mutually-coupled second-order equations. The first-order approximate periodic solution of describing equations is found, obtaining closed-form expressions for both the amplitude and the harmonics of oscillation, as well as for the correction of the oscillation frequency due to the nonlinear effect of varactors. The accuracy of presented formulae was validated by circuit simulations.
{"title":"Large-signal analysis of CMOS - LC VCOs","authors":"A. Buonomo, A. L. Schiavo","doi":"10.1109/ECCTD.2007.4529766","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529766","url":null,"abstract":"A nonlinear perturbation model of a complementary LC-tuned voltage controlled oscillator is derived, which consists of two mutually-coupled second-order equations. The first-order approximate periodic solution of describing equations is found, obtaining closed-form expressions for both the amplitude and the harmonics of oscillation, as well as for the correction of the oscillation frequency due to the nonlinear effect of varactors. The accuracy of presented formulae was validated by circuit simulations.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"467 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123281383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529545
L. Aaltonen, P. Rahikkala, M. Saukoski, K. Halonen
A continuous time analog accelerometer interface is feasible when high dynamic range together with wide signal band is required. This paper provides design data for a 120 dB accelerometer with signal band of 300 Hz. Circuit structures for an integrated interface will be presented and important sources of instabilities discussed. Measured and simulated results will be provided to support the theory.
{"title":"High resolution analog interface for micromachined capacitive accelerometer","authors":"L. Aaltonen, P. Rahikkala, M. Saukoski, K. Halonen","doi":"10.1109/ECCTD.2007.4529545","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529545","url":null,"abstract":"A continuous time analog accelerometer interface is feasible when high dynamic range together with wide signal band is required. This paper provides design data for a 120 dB accelerometer with signal band of 300 Hz. Circuit structures for an integrated interface will be presented and important sources of instabilities discussed. Measured and simulated results will be provided to support the theory.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125328274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529747
M. Bonnin, F. Corinto, M. Gilli, P. Civalleri
The Subharmonic Melnikov's method is a classical tool for the analysis of subharmonic orbits in weakly perturbed nonlinear oscillators, but its application requires the availability of an analytical expression for the periodic trajectories of the unperturbed system. On the other hand, spectral techniques, like the harmonic balance, have been widely applied for the analysis and design of nonlinear oscillators. In this manuscript we show that bifurcations of subharmonic orbits in perturbed systems can be easily detected computing the Melnikov's integral over the harmonic balance approximation of the unperturbed orbits. The proposed method significantly extend the applicability of the Melnikov's method since the orbits of any nonlinear oscillator can be approximated by the harmonic balance technique, and the integrability of the unperturbed system is no more required.
{"title":"Harmonic balance, Melnikov method and nonlinear oscillators under resonant perturbation","authors":"M. Bonnin, F. Corinto, M. Gilli, P. Civalleri","doi":"10.1109/ECCTD.2007.4529747","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529747","url":null,"abstract":"The Subharmonic Melnikov's method is a classical tool for the analysis of subharmonic orbits in weakly perturbed nonlinear oscillators, but its application requires the availability of an analytical expression for the periodic trajectories of the unperturbed system. On the other hand, spectral techniques, like the harmonic balance, have been widely applied for the analysis and design of nonlinear oscillators. In this manuscript we show that bifurcations of subharmonic orbits in perturbed systems can be easily detected computing the Melnikov's integral over the harmonic balance approximation of the unperturbed orbits. The proposed method significantly extend the applicability of the Melnikov's method since the orbits of any nonlinear oscillator can be approximated by the harmonic balance technique, and the integrability of the unperturbed system is no more required.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122580659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529526
G. Gielen, T. Eeckelaert, E. Martens, Trent McConaghy
CMOS technology is evolving deeper and deeper into the nanometer era, which makes the integration of entire systems possible, many of which are mixed-signal in nature, including analog and/or RF parts. This demands for efficient automated synthesis techniques for these analog circuits that include the variability of the circuit parameters. A technique is presented for the efficient yield optimization of analog circuits based on evolution-generated yield models. A hierarchical optimization method is described that optimizes complex circuits based on combining Pareto-optimal performance models in a bottom-up way. Finally, an evolution-based method for the true architectural synthesis of analog systems is presented. This is illustrated with several examples.
{"title":"Automated synthesis of complex analog circuits","authors":"G. Gielen, T. Eeckelaert, E. Martens, Trent McConaghy","doi":"10.1109/ECCTD.2007.4529526","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529526","url":null,"abstract":"CMOS technology is evolving deeper and deeper into the nanometer era, which makes the integration of entire systems possible, many of which are mixed-signal in nature, including analog and/or RF parts. This demands for efficient automated synthesis techniques for these analog circuits that include the variability of the circuit parameters. A technique is presented for the efficient yield optimization of analog circuits based on evolution-generated yield models. A hierarchical optimization method is described that optimizes complex circuits based on combining Pareto-optimal performance models in a bottom-up way. Finally, an evolution-based method for the true architectural synthesis of analog systems is presented. This is illustrated with several examples.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124733421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529662
Byungjin Chun, Zheyao Zhang, S. Lidholm
A circular voltage-controlled phase shifter (VCPS) is proposed to extend the range of the controlled output phase shift unlimitedly. This is made possible by configuring the system to operate in a circular way, differently from the conventional VCPS whose output phase saturates as the phase control input exceeds some value. The circular VCPS is based on a vector modulation method whose modulation signals are generated in a pseudo-sinusoidal way exploiting the current-voltage (I-V) curve of a MOS differential amplifier pair. When the circular VCPS is employed in phase tracking loops, the loop can operate in a stand-alone way thanks to its unlimited phase shifting capability.
{"title":"A circular voltage-controlled phase shifter with unlimited phase range for phase tracking loops","authors":"Byungjin Chun, Zheyao Zhang, S. Lidholm","doi":"10.1109/ECCTD.2007.4529662","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529662","url":null,"abstract":"A circular voltage-controlled phase shifter (VCPS) is proposed to extend the range of the controlled output phase shift unlimitedly. This is made possible by configuring the system to operate in a circular way, differently from the conventional VCPS whose output phase saturates as the phase control input exceeds some value. The circular VCPS is based on a vector modulation method whose modulation signals are generated in a pseudo-sinusoidal way exploiting the current-voltage (I-V) curve of a MOS differential amplifier pair. When the circular VCPS is employed in phase tracking loops, the loop can operate in a stand-alone way thanks to its unlimited phase shifting capability.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123981170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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