P. Furth, Karthik R. Kothapalli, Punith R. Surkanti
{"title":"A high-speed image centroid computation sensor","authors":"P. Furth, Karthik R. Kothapalli, Punith R. Surkanti","doi":"10.1109/MWSCAS.2012.6292027","DOIUrl":null,"url":null,"abstract":"We present a fully-integrated analog CMOS image centroid computation sensor. A 40×40 pixel array is designed and fabricated in a 0.5-μm CMOS process. The proposed centroid computation circuit achieves 7 times improvement in bandwidth compared to similar circuits in the literature. Moreover, the incorporation of a linearized transconductor improves precision in the computed centroid. The sensor is designed to operate over a wide range of photocurrents from 10 pA to 1 μA. Test results of the proposed architecture verify its superior performance.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2012.6292027","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We present a fully-integrated analog CMOS image centroid computation sensor. A 40×40 pixel array is designed and fabricated in a 0.5-μm CMOS process. The proposed centroid computation circuit achieves 7 times improvement in bandwidth compared to similar circuits in the literature. Moreover, the incorporation of a linearized transconductor improves precision in the computed centroid. The sensor is designed to operate over a wide range of photocurrents from 10 pA to 1 μA. Test results of the proposed architecture verify its superior performance.