In-storage embedded accelerator for sparse pattern processing

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-13 DOI:10.1109/HPEC.2016.7761588

S. Jun, H. Nguyen, V. Gadepally, Arvind

引用次数: 9

Abstract

We present a novel architecture for sparse pattern processing, using flash storage with embedded accelerators. Sparse pattern processing on large data sets is the essence of applications such as document search, natural language processing, bioinformatics, subgraph matching, machine learning, and graph processing. One slice of our prototype accelerator is capable of handling up to 1TB of data, and experiments show that it can outperform C/C++ software solutions on a 16-core system at a fraction of the power and cost; an optimized version of the accelerator can match the performance of a 48-core server.

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稀疏模式处理的存储嵌入式加速器

我们提出了一种新的稀疏模式处理架构，使用带有嵌入式加速器的闪存存储。大数据集上的稀疏模式处理是文档搜索、自然语言处理、生物信息学、子图匹配、机器学习和图处理等应用的本质。我们的原型加速器的一个切片能够处理高达1TB的数据，实验表明，它可以在16核系统上以一小部分的功率和成本优于C/ c++软件解决方案;加速器的优化版本可以达到48核服务器的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 IEEE High Performance Extreme Computing Conference (HPEC)

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