Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system

Abstract

This paper presents new techniques for architecture and performance driven compilation of SW programs into RW (reconfigurable HW). These new techniques effectively improve on the complex resource sharing approaches typical of high-level synthesis algorithms, which are efficient for layout flexible ASICs but are clearly not adequate for reconfigurable devices with predefined architectures. The compilation flow takes advantage of a specialized library of circuit-generators and only resorts to logic synthesis for the generation of the data-path's control unit. The algorithms under development are being integrated onto an HW compiler that accepts programs previously compiled to Java/sup TM/ Bytecodes. A series of experiments has been performed using a number of practical examples and the results achieved so far are very promising and indicate that the RW compilation techniques proposed can provide significant improvements over currently available methods.