{"title":"Low noise amplifier linearization for near millimeter wave band applications","authors":"N. Seiedhosseinzadeh, A. Nabavi","doi":"10.1109/MMWATT.2012.6532165","DOIUrl":null,"url":null,"abstract":"In this paper, an improved post linearization technique is presented for high frequency low noise amplifiers (LNAs). It employs two auxiliary diode-connected NMOS-PMOS transistors with a resistor and a capacitor which increases the linearity while partially compensates the gain reduction. This technique improves the IIP3 more than 7 dB by reducing the third-order nonlinearity coefficient of output current. The proposed method has been implemented on a two-stage LNA consisting of a common-source stage and a cascode stage. This LNA has been simulated in a 0.18μm RF CMOS technology consuming only 13.9 mW from a single 1.8-V power supply.","PeriodicalId":297799,"journal":{"name":"2012 Second Conference on Millimeter-Wave and Terahertz Technologies (MMWaTT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Second Conference on Millimeter-Wave and Terahertz Technologies (MMWaTT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MMWATT.2012.6532165","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In this paper, an improved post linearization technique is presented for high frequency low noise amplifiers (LNAs). It employs two auxiliary diode-connected NMOS-PMOS transistors with a resistor and a capacitor which increases the linearity while partially compensates the gain reduction. This technique improves the IIP3 more than 7 dB by reducing the third-order nonlinearity coefficient of output current. The proposed method has been implemented on a two-stage LNA consisting of a common-source stage and a cascode stage. This LNA has been simulated in a 0.18μm RF CMOS technology consuming only 13.9 mW from a single 1.8-V power supply.
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