Technology and design of GaN power devices

2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI:10.1109/ESSDERC.2015.7324714

P. Moens, A. Banerjee, P. Coppens, A. Constant, P. Vanmeerbeek, Z. Li, F. Declercq, L. Schepper, H. Vleeschouwer, C. Liu, B. Padmanabhan, W. Jeon, J. Guo, A. Salih, M. Tack

引用次数: 6

Abstract

This paper reports on the technology and design aspects of an industrial DHEMT process for 650V rated GaN-on-Si power devices, using an in-situ MOCVD grown SiN as surface passivation and gate dielectric, with low interface state density and excellent TDDB. Optimization of the GaN epi stack results in very low off-state leakage (<;10nA/mm). Due to the reduction of buffer trapping, low dynamic Ron (<;10%) is obtained, both at room temperature and at high temperature.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

GaN功率器件的技术与设计

本文介绍了一种采用原位MOCVD生长的SiN作为表面钝化和栅极介质的650V额定GaN-on-Si功率器件的工业DHEMT工艺的技术和设计方面，该工艺具有低界面态密度和优异的TDDB。氮化镓外延层的优化导致极低的断开状态泄漏(< 10nA/mm)。由于缓冲捕获的减少，在室温和高温下均可获得低动态Ron(<;10%)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

2015 45th European Solid State Device Research Conference (ESSDERC)

自引率

0.00%

发文量

期刊最新文献

Experimental analysis of planar edge terminations for high voltage 4H-SiC devices FinFET versus UTBB SOI — A RF perspective Scalability of planar FDSOI and FinFETs and What's in store for the future beyond that? Technology and design of GaN power devices A new physics-based compact model for Bilayer Graphene Field-Effect Transistors