{"title":"Slow-switching-limit loss removal in SC DC-DC converters using adiabatic charging","authors":"Loai G. Salem, Y. Ismail","doi":"10.1109/ICEAC.2011.6136700","DOIUrl":null,"url":null,"abstract":"A novel technique to remove the slow-switching-limit (SSL) loss in switched-capacitor (SC) dc-dc converters is presented. A small series inductor is cascaded with an SC converter causing adiabatic charging of the converter's energy-transfer capacitors. In this work, the theory and necessary conditions for SSL loss elimination through an inductive output filter are derived. The new topology enables high efficiency for on-die dc-dc converters while maintaining reasonable energy density. A 2:1 SC converter is built in 65-nm CMOS process to validate the analysis methods and asses the proposed technique. The proposed adiabatic charging enhances the SC efficiency by 3.3 % with only 13 % area overhead, which otherwise requires doubling the capacitor area.","PeriodicalId":199442,"journal":{"name":"2011 International Conference on Energy Aware Computing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Conference on Energy Aware Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEAC.2011.6136700","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A novel technique to remove the slow-switching-limit (SSL) loss in switched-capacitor (SC) dc-dc converters is presented. A small series inductor is cascaded with an SC converter causing adiabatic charging of the converter's energy-transfer capacitors. In this work, the theory and necessary conditions for SSL loss elimination through an inductive output filter are derived. The new topology enables high efficiency for on-die dc-dc converters while maintaining reasonable energy density. A 2:1 SC converter is built in 65-nm CMOS process to validate the analysis methods and asses the proposed technique. The proposed adiabatic charging enhances the SC efficiency by 3.3 % with only 13 % area overhead, which otherwise requires doubling the capacitor area.
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