M. Bracey, W. Redman-White, J. Hughes, J. Richardson
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引用次数: 13
Abstract
A 70 MS/s CMOS A/D converter is presented. Four double-sampling differential switched-current pipelines are used in a time interleaved structure to achieve a high sampling rate. Particular issues addressed are the matching of signal copies whilst maintaining full analogue bandwidth, and minimising signal corruption during propagation. The experimental converter is fabricated in a standard 0.8 /spl mu/m 5 V digital CMOS process without special options.
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