Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496368
Niu Mengnian, Ding Xinfang, Tao Xiang, Lin Wei
Based on the principle of flow injection analysis (FIA), this paper reports a novel micro FIA-ISFET integrated sensor. Four pairs of long-arm pH-ISFET/REFET units and symmetric Ti/Au film pseudo-reference electrodes are integrated on the chip, so that an integrated configuration of transducer and micro flow-through cell is achieved. The chip size of the sensor is 6*8mm/sup 2/. Initial experimental results indicate that the liquid can be measured driven by peristaltic pump flows with great fluency and that the amount of test sample needed in dynamic measurement is greatly reduced. The integrated sensor has quick response and its reliability and stability are considerably improved.
{"title":"Development of a novel micro FIA-ISFET integrated sensor","authors":"Niu Mengnian, Ding Xinfang, Tao Xiang, Lin Wei","doi":"10.1109/TENCON.1995.496368","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496368","url":null,"abstract":"Based on the principle of flow injection analysis (FIA), this paper reports a novel micro FIA-ISFET integrated sensor. Four pairs of long-arm pH-ISFET/REFET units and symmetric Ti/Au film pseudo-reference electrodes are integrated on the chip, so that an integrated configuration of transducer and micro flow-through cell is achieved. The chip size of the sensor is 6*8mm/sup 2/. Initial experimental results indicate that the liquid can be measured driven by peristaltic pump flows with great fluency and that the amount of test sample needed in dynamic measurement is greatly reduced. The integrated sensor has quick response and its reliability and stability are considerably improved.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"648 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115114243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496358
M. Bracey, W. Redman-White, J. Hughes, J. Richardson
A 70 MS/s CMOS A/D converter is presented. Four double-sampling differential switched-current pipelines are used in a time interleaved structure to achieve a high sampling rate. Particular issues addressed are the matching of signal copies whilst maintaining full analogue bandwidth, and minimising signal corruption during propagation. The experimental converter is fabricated in a standard 0.8 /spl mu/m 5 V digital CMOS process without special options.
{"title":"A 70 MS/s 8-bit differential switched-current CMOS A/D converter using parallel interleaved pipelines","authors":"M. Bracey, W. Redman-White, J. Hughes, J. Richardson","doi":"10.1109/TENCON.1995.496358","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496358","url":null,"abstract":"A 70 MS/s CMOS A/D converter is presented. Four double-sampling differential switched-current pipelines are used in a time interleaved structure to achieve a high sampling rate. Particular issues addressed are the matching of signal copies whilst maintaining full analogue bandwidth, and minimising signal corruption during propagation. The experimental converter is fabricated in a standard 0.8 /spl mu/m 5 V digital CMOS process without special options.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115318673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496338
G. Kuang, Zhan-guo Wang, Jiben Liang, Bowei Xu, Zhanping Zhu, L. Zou
For the first time, we have grown (Al,Ga)As/GaAs epilayers which show some remarkable quantum wire characteristics-red shift as much as 98 meV-on vicinal (111)B GaAs substrate. For comparison, the epilayers were also deposited on (100) and (111)B substrates simultaneously. But the PL results of these three samples are very different-we explained these PL results with a model based on growth dynamics and drew a conclusion that steps on (111)B surface can play a very important role in crystal growth.
{"title":"PL study of (Al,Ga)As epilayers grown on (100), (111)B and vicinal (111)B GaAs substrates","authors":"G. Kuang, Zhan-guo Wang, Jiben Liang, Bowei Xu, Zhanping Zhu, L. Zou","doi":"10.1109/TENCON.1995.496338","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496338","url":null,"abstract":"For the first time, we have grown (Al,Ga)As/GaAs epilayers which show some remarkable quantum wire characteristics-red shift as much as 98 meV-on vicinal (111)B GaAs substrate. For comparison, the epilayers were also deposited on (100) and (111)B substrates simultaneously. But the PL results of these three samples are very different-we explained these PL results with a model based on growth dynamics and drew a conclusion that steps on (111)B surface can play a very important role in crystal growth.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127148826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496429
L. Sabesan, P. Mawby, M. Towers, K. Board, P. Waind
The modelling of steady-state characteristics in a trench emitter IGBT structure is presented. The semiconductor equations were solved in two dimensions with physical effects such as carrier-carrier scattering mobility, SRH and Auger recombination included. The I-V characteristics, internal characteristics forward voltage drop and latch-up characteristics have been investigated. Comparison between simulation and measurement have shown a good agreement.
{"title":"Analysis of non-punch through trench emitter insulated gate bipolar transistor (IGBT)","authors":"L. Sabesan, P. Mawby, M. Towers, K. Board, P. Waind","doi":"10.1109/TENCON.1995.496429","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496429","url":null,"abstract":"The modelling of steady-state characteristics in a trench emitter IGBT structure is presented. The semiconductor equations were solved in two dimensions with physical effects such as carrier-carrier scattering mobility, SRH and Auger recombination included. The I-V characteristics, internal characteristics forward voltage drop and latch-up characteristics have been investigated. Comparison between simulation and measurement have shown a good agreement.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117254161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496446
Seung Ho Lee, B. Y. Choi, M. Lee
This paper describes the HDL based design of a RISC microprocessor for portable workstation which especially requires both cost effectiveness and highly integrated functions. Based on 0.6 /spl mu/m TLM CMOS technology, this chip includes IU, MMU/CC, bus controller, and address translation memory in a 1.1 cm/sup 2/ die size, and operates at 45 MHz. Both fast design time and the easiness of full functional verification could be feasible with standard cell based design methodology and pseudo system modelling.
{"title":"ASIC implementation of a RISC microprocessor for portable workstation","authors":"Seung Ho Lee, B. Y. Choi, M. Lee","doi":"10.1109/TENCON.1995.496446","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496446","url":null,"abstract":"This paper describes the HDL based design of a RISC microprocessor for portable workstation which especially requires both cost effectiveness and highly integrated functions. Based on 0.6 /spl mu/m TLM CMOS technology, this chip includes IU, MMU/CC, bus controller, and address translation memory in a 1.1 cm/sup 2/ die size, and operates at 45 MHz. Both fast design time and the easiness of full functional verification could be feasible with standard cell based design methodology and pseudo system modelling.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129620338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496348
Wen-Chau Liu, J. Tsai, Lih-Wen, K. Thei, Chang-Zn Wu, W. Lour, Yuan-Tzu, Rong-Chau Liu
A fabricated camel-gate FET with a tri-step doping channel exhibits a large drain current density of >750 mA/mm. Furthermore, the relatively voltage-independent transconductance is as high as 220 mS/mm and the applied gate voltage is of up to +1.5 V. A 1.5/spl times/100 /spl mu/m/sup 2/ gate dimension device was found to have a f/sub T/ of about 30 GHz with very low input capacitance.
{"title":"GaAs tri-step high-low doping channel field effect transistor","authors":"Wen-Chau Liu, J. Tsai, Lih-Wen, K. Thei, Chang-Zn Wu, W. Lour, Yuan-Tzu, Rong-Chau Liu","doi":"10.1109/TENCON.1995.496348","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496348","url":null,"abstract":"A fabricated camel-gate FET with a tri-step doping channel exhibits a large drain current density of >750 mA/mm. Furthermore, the relatively voltage-independent transconductance is as high as 220 mS/mm and the applied gate voltage is of up to +1.5 V. A 1.5/spl times/100 /spl mu/m/sup 2/ gate dimension device was found to have a f/sub T/ of about 30 GHz with very low input capacitance.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130321302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496374
M. Jeng, Zhihong Liu, Yuhua Cheng
This paper describes recent activities and trends in MOSFET modeling. Both the DC and AC aspects of MOSFET models are covered. Due to the more stringent requirements, test procedures for both analog and digital applications have been proposed. Existing SPICE models are evaluated against these tests. In particular, BSIM3 and MOS9, the two mostly discussed candidates for the standard deep-submicron MOSFET model, are compared.
{"title":"Deep-submicron MOSFET modeling for circuit simulation","authors":"M. Jeng, Zhihong Liu, Yuhua Cheng","doi":"10.1109/TENCON.1995.496374","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496374","url":null,"abstract":"This paper describes recent activities and trends in MOSFET modeling. Both the DC and AC aspects of MOSFET models are covered. Due to the more stringent requirements, test procedures for both analog and digital applications have been proposed. Existing SPICE models are evaluated against these tests. In particular, BSIM3 and MOS9, the two mostly discussed candidates for the standard deep-submicron MOSFET model, are compared.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123936702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496409
L. Ng, C.C. Jong
This paper presents a software system for implementing synthesized digital designs using VHDL so that the designs can be accepted by existing CAD systems to achieve low-level verification such as delay analysis and logic simulation as well as layout realization in various technologies.
{"title":"Implementation of synthesized digital systems with VHDL","authors":"L. Ng, C.C. Jong","doi":"10.1109/TENCON.1995.496409","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496409","url":null,"abstract":"This paper presents a software system for implementing synthesized digital designs using VHDL so that the designs can be accepted by existing CAD systems to achieve low-level verification such as delay analysis and logic simulation as well as layout realization in various technologies.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114323334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496396
M. Chan, T. Lo
A planar Au metallization process by electrolytic plating has been developed for metal interconnections in the submicron range. Gold wires with high aspect ratio were fabricated in an embedded structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the gold wires can be selectively formed within the dielectric. This process can provide desired properties of conductor structures for Si LSI applications.
{"title":"Electrochemical planarization by selective electroplating for embedded gold wiring in the sub-micron range","authors":"M. Chan, T. Lo","doi":"10.1109/TENCON.1995.496396","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496396","url":null,"abstract":"A planar Au metallization process by electrolytic plating has been developed for metal interconnections in the submicron range. Gold wires with high aspect ratio were fabricated in an embedded structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the gold wires can be selectively formed within the dielectric. This process can provide desired properties of conductor structures for Si LSI applications.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"2002 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125756939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-06DOI: 10.1109/TENCON.1995.496408
R.M.M. Chen, X. D. Jia, L. Han
In this paper, a new technique to improve the convergency characteristics of relaxation-based methods for circuit simulations is presented. The technique may overcome the difficulty of slow convergence or non-convergence characteristics of relaxation-based circuit simulation methods when a circuit contains strongly coupled components or feedback loops. Two numerical examples are given to show the effectiveness of the technique.
{"title":"Convergency improvement for relaxation-based circuit simulations","authors":"R.M.M. Chen, X. D. Jia, L. Han","doi":"10.1109/TENCON.1995.496408","DOIUrl":"https://doi.org/10.1109/TENCON.1995.496408","url":null,"abstract":"In this paper, a new technique to improve the convergency characteristics of relaxation-based methods for circuit simulations is presented. The technique may overcome the difficulty of slow convergence or non-convergence characteristics of relaxation-based circuit simulation methods when a circuit contains strongly coupled components or feedback loops. Two numerical examples are given to show the effectiveness of the technique.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125989498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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