Achieving page-mapping FTL performance at block-mapping FTL cost by hiding address translation

Yang Hu, Hong Jiang, D. Feng, Lei Tian, Shu Ping Zhang, Jingning Liu, Wei Tong, Yi Qin, Liuzheng Wang
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引用次数: 57

Abstract

Flash Translation Layer (FTL) is one of the most important components of SSD, whose main purpose is to perform logical to physical address translation in a way that is suitable to the unique physical characteristics of the Flash memory technology. The pure page-mapping FTL scheme, arguably the best FTL scheme due to its ability to map any logical page number (LPN) to any physical page number (PPN) to minimize erase operations, cannot be practically deployed since it consumes a prohibitively large RAM (SRAM or DRAM) space to store the page-mapping table for an SSD of moderate to large size. Alternatives to the pure page-mapping FTL, such as block-mapping FTLs, hybrid FTLs (e.g., FAST) and the latest demand-based page-mapping FTLs (e.g., DFTL), require significantly less RAM space but suffer from a few performance issues. Block-mapping FTLs perform poorly with higher erasure counts, particularly under random write workloads. Hybrid FTL schemes incur costly merge operations that hurt performance and increase the erasure counts. Performances of demand-based FTLs heavily depend on workload characteristics such as access locality, read/write ratio and request arrival interval time. This paper proposes a new FTL scheme, called HAT, to achieve the performance of a pure page-mapping FTL at the RAM cost of a block-mapping FTL while consuming lower energy, by hiding the address translation (HAT). The basic idea behind our scheme is to create a separate access path to read/write the address mapping information to significantly Hide the Address-Translation latency by incorporating a low energy-consuming solid-state memory device that stores the entire page mapping table. We implement an SSD simulator, SSDsim, to validate our HAT design and evaluate its performance. The extensive trace-driven simulation results show that the performance of HAT is within 0.8% of the pure page-mapping FTL, while consuming about 50% of the energy.
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通过隐藏地址转换,以块映射FTL为代价实现页映射FTL性能
Flash Translation Layer (FTL)是SSD最重要的组成部分之一,其主要作用是根据闪存技术独特的物理特性,完成逻辑地址到物理地址的转换。纯粹的页面映射FTL方案,可以说是最好的FTL方案,因为它能够将任何逻辑页码(LPN)映射到任何物理页码(PPN),以最小化擦除操作,不能实际部署,因为它消耗了非常大的RAM (SRAM或DRAM)空间来存储中等到大尺寸的SSD的页面映射表。纯页面映射FTL的替代方案,如块映射FTL、混合FTL(例如FAST)和最新的基于需求的页面映射FTL(例如DFTL),需要的RAM空间显著减少,但存在一些性能问题。块映射ftl在更高的擦除计数下表现不佳,特别是在随机写工作负载下。混合FTL方案会导致代价高昂的合并操作,这会损害性能并增加擦除计数。基于需求的ftl的性能在很大程度上取决于工作负载特征,如访问位置、读/写比率和请求到达间隔时间。本文提出了一种新的FTL方案,称为HAT,通过隐藏地址转换(HAT),以块映射FTL的RAM成本实现纯页面映射FTL的性能,同时消耗更低的能量。我们的方案背后的基本思想是创建一个单独的访问路径来读/写地址映射信息,通过结合存储整个页面映射表的低能耗固态内存设备来显着隐藏地址转换延迟。我们实现了一个SSD模拟器SSDsim来验证我们的HAT设计并评估其性能。广泛的跟踪驱动仿真结果表明,HAT的性能在纯页面映射FTL的0.8%以内,而能耗约为50%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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Automated lookahead data migration in SSD-enabled multi-tiered storage systems Write amplification reduction in NAND Flash through multi-write coding Leveraging disk drive acoustic modes for power management Achieving page-mapping FTL performance at block-mapping FTL cost by hiding address translation Energy and thermal aware buffer cache replacement algorithm
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