A 110 mhz Mpeg2 Variable Length Decoder LSI

Komoto, Masataka Seguchi
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一个110兆赫Mpeg2可变长度解码器LSI
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Circuit Techniques For An 8-ns Ecl 100K Compatible 3.3v 16mb Bicmos Sram With Minimum Operation Voltage Of 2.3v A 15- 150mhz, All-Digital Phase-Locked Loop with 50-Cycle Lock Time for High-Performance Low-Power Microprocessors A Digital Self Compensation Circuit for High Speed D/a Converters A 110 mhz Mpeg2 Variable Length Decoder LSI A 200mhz 16mbit Synchronous Dram With Block Access Mode
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