Hardware implementation of a memory allocator

Abstract

It is generally felt that the complexity of system-on-chip (SOC) can only be addressed by intellectual-property (IP) based design. While IPs such as processor cores, memories, and bus controllers are being offered by many vendors, IP cores for dynamic memory management, an important task for any complex application, have been close to non-existent. This paper describes the implementation of a buddy system based soft IP core after a review of common memory allocation algorithms. The study also investigates the impact of different IP configuration and different synthesis strategies on the synthesis quality.