Hardware acceleration of divide-and-conquer paradigms: a case study

[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines Pub Date : 1993-04-05 DOI:10.1109/FPGA.1993.279463

W. Luk, V. Lok, I. Page

引用次数: 24

Abstract

The authors describe a method for speeding up divide-and-conquer algorithms with a hardware coprocessor, using sorting as an example. The method employs a conventional processor for the 'divide' and 'merge' phases, while the 'conquer' phase is handled by a purpose-built coprocessor. It is shown how transformation techniques from the Ruby language can be adopted in developing a family of systolic sorters, and how one of the resulting designs is prototyped in eight FPGAs on a PC coprocessor board known as CHS2*4 from Algotronix. The execution of the hardware unit is embedded in a sorting program, with the PC host merging the sorted sequences from the hardware sorter. The performance of this implementation is compared against various sorting algorithms on a number of PC systems.<>

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

分而治之范式的硬件加速:一个案例研究

作者描述了一种用硬件协处理器加速分治算法的方法，并以排序为例。该方法使用传统处理器处理“分割”和“合并”阶段，而“征服”阶段由专用协处理器处理。它展示了Ruby语言的转换技术如何用于开发一系列收缩分选器，以及如何在Algotronix的称为CHS2*4的PC协处理器板上的8个fpga中原型化其中一个结果设计。硬件单元的执行嵌入在排序程序中，PC主机合并来自硬件排序器的排序序列。将此实现的性能与许多PC系统上的各种排序算法进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines

自引率

0.00%

发文量

期刊最新文献

Virtual wires: overcoming pin limitations in FPGA-based logic emulators The CM-2X: a hybrid CM-2/Xilinx prototype Hardware acceleration of divide-and-conquer paradigms: a case study Data-folding in SRAM configurable FPGAs WASMII: a data driven computer on a virtual hardware