FPGA prototype design of the computation nodes in a cluster based MPSoC

Abstract

With the improved performance of SoC for real-time application, more and more processing cores have been integrated into one chip, which is called MPSoC. One of the key problems is how to design the MPSoC architecture to improve the overall performance. In this paper, a cluster-based MPSoC using hierarchical on-chip communication is proposed. In the top level, on-chip network is used as the communication backbone for various clusters. In the cluster level, processing cores and IPs communicate with each others via a hierarchical bus. This paper focuses on the design and verification problems of computation cluster, which consists of several RISC processors and storage components. Separate control path and data path are designed to meet the performance requirements. The proposed architecture is implemented into a FPGA prototype. And a video application is mapped on the prototype to verify the functionality. Experiments show that the proposed MPSoC can work at 90 MHz and successfully accomplish real-time fade-in-fade-out processing of 4 lane videos which are 320⋆240 and 24 frames per second.