Y. Nakakura, T. Yoshida, H. Nakano, M. Nakajima, Y. Goi, Y. Nakai, R. Segawa, T. Kishida, S. Kameyama, H. Kadota
{"title":"Design methodology for over 100MFLOPS 64bit MPU with 0.8/spl mu/m BiCMOS technology","authors":"Y. Nakakura, T. Yoshida, H. Nakano, M. Nakajima, Y. Goi, Y. Nakai, R. Segawa, T. Kishida, S. Kameyama, H. Kadota","doi":"10.1109/VLSIC.1991.760059","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":319036,"journal":{"name":"1991 Symposium on VLSI Circuits","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1991 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1991.760059","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
