A 0.7-1 Gb/s CMOS clock recovery circuit

Abstract

A 0.7-1 Gb/s clock recovery circuit is designed by ruing a 0.5 /spl mu/m digital CMOS process. It consists of a bang-bang type frequency detector (FD) to acquire frequency lock and a linear phase detector (PD) to acquire phase lock. The FD is able to reset itself upon frequency lock. Measured RMS jitter of the recovered clock is 7.4 ps at 1 GHz and 7 ps at 0.7 GHz. It is able to maintain a BER better than 10/sup -11/ for up to 140 missing transitions. It consumes 200 mW with a 5 V power supply.