{"title":"A compact I/Q imbalance calibration technique for power-aware fully-integrated receiver without on-chip baseband processor","authors":"Mo Huang, Xiaofeng Liang, Jianping Guo, Dihu Chen","doi":"10.1109/IEEE-IWS.2015.7164512","DOIUrl":null,"url":null,"abstract":"The in-phase and quadrature (I/Q) calibration has been typically implemented in DSP/MCU to reject image in receive chain. In this work, a compact, fully-integrated calibration technique is proposed without the need of baseband processors, which is very suitable for low-power low-cost wireless applications. By making use of the transmitter (TX) phase loop lock (PLL) in frequency duplex division (FDD) mode, a clean, compact calibration source is implemented with only 0.069mm2 extra area. The proposed calibration technique has been applied to an FDD transceiver in 0.13-μm CMOS technology. The measurements show that with the proposed calibration, a -60-dBc image rejection ratio (IRR), a minimum 1.7% error vector magnitude (EVM), and a 26-μs calibration time are achieved.1","PeriodicalId":164534,"journal":{"name":"2015 IEEE International Wireless Symposium (IWS 2015)","volume":"238 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Wireless Symposium (IWS 2015)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEEE-IWS.2015.7164512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The in-phase and quadrature (I/Q) calibration has been typically implemented in DSP/MCU to reject image in receive chain. In this work, a compact, fully-integrated calibration technique is proposed without the need of baseband processors, which is very suitable for low-power low-cost wireless applications. By making use of the transmitter (TX) phase loop lock (PLL) in frequency duplex division (FDD) mode, a clean, compact calibration source is implemented with only 0.069mm2 extra area. The proposed calibration technique has been applied to an FDD transceiver in 0.13-μm CMOS technology. The measurements show that with the proposed calibration, a -60-dBc image rejection ratio (IRR), a minimum 1.7% error vector magnitude (EVM), and a 26-μs calibration time are achieved.1
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