Design and Analysis of a Novel High Speed Adder Based Hardware Efficient Discrete Cosine Transform (DCT)

Abstract

In this paper we have designed high speed Adder based hardware efficient Discrete Cosine Transform (DCT) Algorithm, which process data in a sequential form at high data rate. We designed a novel DCT by using orthogonal property and compared with conventional DCT in terms of number of cells, cell area, leakage power, internal power, net power, switching power, delay and power delay product (PDP). In comparison with multiplier based conventional DCT and Adder based Conventional DCT, the net power dissipation is reduced by 32%. The proposed Adder based DCT net power Dissipation is reduced by 47% less and multiplier based proposed DCT is reduced by 38%. Here we have used Cadence RTL 180nm Technology to implement the design.