{"title":"On-chip DC-DC voltage down converter for low-power IC chip","authors":"Qianneng Zhou, Mingyan Yu, Jianguo Ma, Y. Ye","doi":"10.1109/ICASIC.2005.1611332","DOIUrl":null,"url":null,"abstract":"This paper presents a novel on-chip DC-DC voltage down converter (VDC): a temperature-independence reference voltage generator and a voltage-up converter. The architecture of the proposed VDC is simple, and can be fabricated by conventional CMOS technology. For 5 V to 3.3 V conversions, it provides an output voltage insusceptible to external supply-voltage bouncing, temperature variation, and load current variation. A temperature dependency of only 0.65 mV//spl deg/C and a voltage deviation within /spl plusmn/0.16% for /spl plusmn/10% variation of external supply voltage are achieved. The voltage is stabilized with /spl plusmn/17 mV for load current varying from 0 to 100 mA.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611332","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a novel on-chip DC-DC voltage down converter (VDC): a temperature-independence reference voltage generator and a voltage-up converter. The architecture of the proposed VDC is simple, and can be fabricated by conventional CMOS technology. For 5 V to 3.3 V conversions, it provides an output voltage insusceptible to external supply-voltage bouncing, temperature variation, and load current variation. A temperature dependency of only 0.65 mV//spl deg/C and a voltage deviation within /spl plusmn/0.16% for /spl plusmn/10% variation of external supply voltage are achieved. The voltage is stabilized with /spl plusmn/17 mV for load current varying from 0 to 100 mA.