Power reduction in high-speed inter-chip data communications

Abstract

This paper describes power reduction techniques in high-speed inter-chip data communication with inductive coupled wireless interface for 3D-stacked SiP. NRZ signaling where signal is not transmitted when data holds reduces power dissipation in proportion to switching activity. A low-power single-end transmitter is presented for 55% transmitter's power reduction. Depending on communication distance, transmit power is controlled for both power and crosstalk reduction. 195Gb/s, 1.2W high-speed and low-power interface with these techniques has been demonstrated in 0.25mum CMOS