{"title":"Design of error-compensated fixed-width multiplier","authors":"Aniket V. Junghare, R. Keote, P. Karule","doi":"10.1109/ICCSP.2015.7322804","DOIUrl":null,"url":null,"abstract":"This paper presents an error compensation method for fixed-width multipliers. The analysis for the truncation part is done and accordingly the compensation circuit is made. Here design of 6-bit fixed-width multiplier is done using Xilinx. The simulation results show significant improvement in terms of delay and also save area.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Conference on Communications and Signal Processing (ICCSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCSP.2015.7322804","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents an error compensation method for fixed-width multipliers. The analysis for the truncation part is done and accordingly the compensation circuit is made. Here design of 6-bit fixed-width multiplier is done using Xilinx. The simulation results show significant improvement in terms of delay and also save area.
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